Semiconductor Package Pad Layout for Curvature and Stack Void Reduction
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Solution Overview
Problem
The increasing demand for high integration and high-speed semiconductor devices poses challenges in maintaining process margins and reducing voids during chip stacking, as existing technologies struggle with curvature in topography and stack voids due to the complexity of multilayer metal patterns and insulating layers.
Innovation Solution
The semiconductor device design incorporates multilayer metal patterns and insulating layers with strategically arranged electrode and alleviation patterns, where the ratio of alleviation patterns changes with distance from the edge, minimizing curvature and voids by hybrid bonding and using dummy pads to alleviate topography, thereby enhancing product reliability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multilayer metal patterns and insulating layers are used to achieve high integration, then device functionality is improved, but curvature and stack voids increase during chip stacking
Solution Approach 1:
The uppermost metal layer is segmented into two functional types: electrode patterns for signal transfer and alleviation patterns for curvature compensation. This segmentation allows the same layer to simultaneously maintain electrical functionality while compensating for topography-induced curvature, thereby reducing stack voids during chip stacking.
Solution Approach 2:
Different regions of the uppermost metal layer are assigned different functions: electrode patterns in signal-critical regions maintain high conductivity, while alleviation patterns in non-critical regions provide curvature compensation. The density and distribution of these patterns are locally optimized based on the specific topography and electrical requirements of each region.
2Adaptability or versatility
If multilayer metal patterns and insulating layers are used to achieve high integration, then device functionality is improved, but process margin decreases
Solution Approach 1:
Instead of requiring all metal patterns to maintain perfect flatness, the patent applies partial compensation through alleviation patterns only in regions where topography-induced curvature affects manufacturing precision. This partial action approach maintains adequate process margins without requiring excessive compensation across the entire structure.
3Speed
If electrode patterns are densely arranged to achieve high speed, then signal transfer capability is improved, but curvature and voids increase
Solution Approach 1:
The metal layer is segmented into electrode patterns for signal transfer and alleviation patterns for curvature compensation. This allows dense electrode patterns to be arranged for high-speed signal transfer while separate alleviation patterns compensate for the curvature and voids that would otherwise result from such dense arrangement.
Data Source
AI summary
There is provided a semiconductor device with improved product reliability. The semiconductor device includes a substrate, a structure on the substrate and including multilayer metal patterns and multilayer insulating layers, and a pad layer on the structure and including a plurality of bonding pads, wherein a plurality of uppermost patterns at an uppermost layer among the multilayer metal patterns include electrode patterns for transferring signals and alleviation patterns that do not transfer the signals, a first ratio of the alleviation patterns within a first reference shape at a first distance from an edge of the structure is greater than a second ratio of the alleviation patterns within a second reference shape at a second distance from the edge of the structure, and the first distance is greater than the second distance.