Semiconductor Package Pad Offset Layout for Dual-Speed Probe Testing
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Solution Overview
Problem
Current semiconductor device packaging technologies face challenges in accommodating both low-speed and high-speed testing requirements, leading to increased production costs and cycle times due to the need for separate probe cards and testing processes.
Innovation Solution
A package structure with an isolation layer and multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer, where the center points of second pads are offset relative to first pads, allowing for the same probe card to perform both low-speed and high-speed tests without replacing the probe card.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate probe cards are used for low-speed and high-speed testing, then testing accuracy is improved, but device complexity and production cost increase
Solution Approach 1:
The patent implements a universal probe card design where the same probe card can perform both low-speed and high-speed testing by utilizing different pad configurations (first pads for low-speed, second pads for high-speed). This multi-functional approach eliminates the need for separate probe cards while maintaining testing accuracy for both speed regimes, directly resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent segments the testing function into different pad groups (first pads and second pads) that can be selectively activated based on testing requirements. By dividing the pad structure into functional segments, the system achieves both low-speed and high-speed testing capabilities through a single probe card, reducing overall system complexity while preserving measurement precision
2Reliability
If separate probe cards are used for low-speed and high-speed testing, then testing reliability is improved, but loss of time increases
Solution Approach 1:
The patent merges the low-speed and high-speed testing functions into a single probe card system. By combining both testing capabilities in one unified device, the production cycle is shortened as there is no need to replace probe cards between test types, while reliability is maintained through dedicated pad configurations for each testing mode
Solution Approach 2:
The probe card is pre-configured with both first pads and second pads during manufacturing, allowing immediate switching between low-speed and high-speed testing modes without requiring preliminary probe card replacement actions. This preliminary preparation eliminates time loss while ensuring testing reliability through proper pad-probe alignment
3Adaptability or versatility
If multiple pad configurations are integrated in one package structure, then adaptability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating distinct pad regions (first pads and second pads) with specific geometric and positional characteristics optimized for their respective testing functions. Each pad group maintains its own quality standards while being integrated into a unified structure, allowing high adaptability without compromising manufacturing precision through localized optimization
Data Source
AI summary
A package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each via exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each first pad is formed by a respective part of the interconnection layer exposed by the corresponding via, N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer is formed on the RDLs and exposes a part area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad.