Semiconductor Bonding Pad Overlap Structure for Stress Relief
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Solution Overview
Problem
The integration of semiconductor devices leads to a reduction in electrical properties and production yield, necessitating improvements in reliability and performance to meet the demands of high-speed and low-voltage electronic products.
Innovation Solution
A semiconductor device design featuring overlapping pad and dielectric layer structures, with protrusions, that minimizes stress and delamination by creating specific overlap sections and spaces between bonding structures, allowing for efficient electrical connections and enhanced reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration of semiconductor devices is increased, then the functionality and compactness are improved, but the electrical properties and production yield deteriorate
Solution Approach 1:
The bonding structure is divided into multiple sections including a bonding pad, a bonding dielectric layer, and a via structure. The via structure is further segmented into a via hole and a via plug, allowing for independent optimization of each component to maintain electrical properties while achieving high integration.
Solution Approach 2:
The bonding dielectric layer has different properties in different regions: it provides insulation in the bulk while allowing for controlled stress distribution near the bonding interface. The via structure provides localized electrical connection while the surrounding dielectric provides mechanical support and stress relief.
2Reliability
If stress and delamination are minimized through overlapping structures, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The bonding pad, bonding dielectric layer, and via structure are merged into an integrated bonding structure. The dielectric layer extends continuously from the pad edge, and the via structure is integrated within this extended region, creating a unified structure that provides both mechanical stability and electrical connectivity without requiring separate components.
Solution Approach 2:
The bonding dielectric layer extends not only in the planar direction from the pad edge but also in the vertical direction, creating a three-dimensional overlapping region. This vertical extension allows for stress distribution in multiple dimensions, improving reliability without requiring complex lateral structures.
Data Source
AI summary
Disclosed is a semiconductor device comprising an upper pad surrounded by an upper dielectric layer, a lower pad in contact with the upper pad and the upper dielectric layer surrounded by a lower dielectric layer. The upper pad, the upper dielectric layer, the lower pad, and the lower dielectric layer define an upper space surrounding a lower portion of the upper pad and a lower space surrounding an upper portion of the lower pad. The upper space includes a first pad overlap section overlapping the lower pad and a first dielectric layer overlap section overlapping the lower dielectric layer. The lower pad includes a first protrusion part protruding toward the first pad overlap section of the upper space. The first protrusion part of the lower pad is at a level higher than that of a bottom surface of the upper dielectric layer.