Semiconductor Pad Perimeter Doping for 3D Memory Resistance
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Solution Overview
Problem
High resistance in semiconductor pads of three-dimensional memory devices leads to slower operation and complex control circuitry due to varying current paths across the array, especially in large arrays with multiple layers.
Innovation Solution
The implementation of semiconductor pads with outside and inside perimeter lower resistance regions formed by impurity implantation at specific angles, reducing electrical resistance and creating low resistance paths for efficient interconnects across multiple layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor pads are used in 3D memory devices, then the device structure is simple, but the electrical resistance is high leading to slower operation
Solution Approach 1:
The patent applies local quality by creating perimeter lower resistance regions around the semiconductor pads through selective impurity implantation. This modifies only the peripheral areas of the pads to have lower resistance than the interior regions, optimizing current flow paths without altering the entire pad structure. The selective modification of specific zones (perimeter vs interior) directly addresses the high resistance problem while maintaining overall structural integrity.
Solution Approach 2:
The patent changes the electrical resistance parameter by implanting impurities at specific angles and energies to create doped regions with lower resistance. The impurity concentration, implantation angle, and energy are carefully controlled to achieve the desired resistance reduction in the perimeter regions while maintaining appropriate resistance in the interior regions for proper device operation.
2Device complexity
If conventional pads with uniform resistance are used, then the manufacturing process is simple, but the current paths vary across the array making control circuitry complex
Solution Approach 1:
By creating uniform perimeter lower resistance regions around all pads in the array, the patent ensures consistent current flow characteristics across all memory cells. This local modification at each pad perimeter creates uniformity in current paths throughout the array, simplifying control and sensing circuitry design while maintaining a relatively straightforward manufacturing process using standard ion implantation techniques.
3Speed
If the pad resistance is reduced uniformly across the entire pad, then the operation speed improves, but the manufacturing precision requirements increase
Solution Approach 1:
The patent reduces manufacturing precision requirements by limiting the impurity implantation to perimeter regions only, rather than requiring uniform doping across the entire pad. The ion implantation is directed at specific angles to confine the doped regions to the pad perimeters, which is easier to control and achieve with standard manufacturing equipment compared to achieving uniform doping across the whole pad area.
Solution Approach 2:
The patent segments the pad into two distinct regions: perimeter lower resistance regions and interior regions. This segmentation allows different resistance characteristics in different zones, with the perimeter regions optimized for current flow and the interior regions maintaining appropriate electrical properties. The segmentation is achieved through angularly directed impurity implantation that naturally confines doping to peripheral zones.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower resistance connections and more consistent operating characteristics across the device, enabling high-speed operations and simplified control circuitry in high-density 3D memory devices.
Implementation Method 1
The outside perimeter lower resistance regions can be formed, according to embodiments of the technology described herein, by implanting impurities directed at one or more angles away from normal into a patterned stack of pads
Data Source
AI summary
A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.