Semiconductor Package Pad Pattern Recess for Stacked Chip Height
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing height and enhancing reliability, particularly in stacked chip configurations where electrical short failures and increased height hinder performance and storage capacity.
Innovation Solution
The semiconductor package design incorporates a through via structure and pad pattern with a recessed configuration, allowing for reduced gap height between chips and minimizing electrical short failures by bonding bump patterns within the recessed areas, thereby enabling a more compact and reliable stacked structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flat pad patterns are used for bonding, then the bonding process is simple, but the package height increases and electrical short failures occur more frequently
Solution Approach 1:
The pad pattern is segmented into multiple functional zones: a recessed region that receives the bump pattern, a raised region that provides bonding surface, and a flat region. This segmentation allows the bump pattern to be embedded within the recessed area, reducing package height while maintaining reliable electrical connections and preventing short failures between adjacent bumps.
Solution Approach 2:
The pad pattern transitions from a conventional two-dimensional flat surface to a three-dimensional structure with recessed and raised regions. This dimensional change allows the bump pattern to be positioned at a lower height relative to the substrate, reducing the overall package height while maintaining proper electrical connectivity through the via structures.
2Reliability
If chips are stacked with larger gaps for reliable bonding, then bonding reliability improves, but the overall package height increases
Solution Approach 1:
The bump pattern is nested within the recessed region of the pad pattern, similar to a doll within a doll. This nesting arrangement allows the bump pattern to be embedded rather than sitting on top of a flat surface, reducing the vertical space required for bonding while maintaining reliable electrical connections through the via structures that extend through the substrate.
3Reliability
If the pad pattern is made larger to ensure proper bonding contact, then bonding reliability improves, but the area available for additional chips decreases
Solution Approach 1:
The pad pattern exhibits local quality variations with different regions serving different functions: the recessed region provides embedding space for the bump pattern, the raised region ensures adequate bonding contact area, and the via structures provide electrical connectivity. This localized functional differentiation allows reliable bonding without requiring an overall increase in pad pattern area, preserving substrate space for additional chips.
Data Source
AI summary
A semiconductor package may include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a through via structure and a pad pattern. The first semiconductor substrate may include a first surface and a second surface opposite to the first surface, and the second surface may include a recess. The through via structure may pass through the first semiconductor substrate from the first surface to a bottom of the recess of the second surface. An upper surface of the through via structure may protrude from the bottom of the recess. The pad pattern may be electrically connected to the upper surface of the through via structure, and the pad pattern may include a first recess having a concave shape thereon. The second semiconductor chip may include a bump pattern bonded on an inside of the first recess of the pad pattern.