Semiconductor Package Pad Segmentation for Bonding Reliability
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Solution Overview
Problem
Conventional semiconductor packaging techniques face challenges with increasing I/O pins due to limitations in wire bonding and solder bump arrays, including poor mechanical adhesion, oxide layer formation, and intermetallic compound vulnerabilities, which affect the reliability and efficiency of semiconductor devices.
Innovation Solution
A semiconductor package design featuring a substrate with a chip pad, redistributed lines, and external terminal connection pads, where barrier layers prevent diffusion of ingredients from the redistributed lines into the pads, and a passivation layer exposes the chip pad for electrical connections, allowing for both solder bumps and bonding wires to be connected uniformly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single pad structure is used for both solder bump and wire bonding connections, then device complexity is reduced, but material adhesion and bonding reliability deteriorate due to conflicting material requirements
Solution Approach 1:
The pad structure is segmented into multiple functional zones: a first pad region for solder bump connections and a second pad region for wire bonding connections. This segmentation allows each region to be optimized for its specific function with appropriate material compositions, resolving the conflict between simplified structure and bonding reliability.
Solution Approach 2:
Different material compositions and structures are applied to different regions of the pad. The first pad region contains materials optimized for solder bump adhesion, while the second pad region contains materials optimized for wire bonding. This local differentiation enables both connection types to achieve reliable bonding without compromising the other.
2Adaptability or versatility
If the number of I/O pins is increased to enhance device functionality, then adaptability improves, but manufacturing precision deteriorates due to minimum bond pitch limitations
Solution Approach 1:
The pad structure utilizes vertical layering and three-dimensional configuration to increase I/O pin capacity. By stacking multiple pad regions and using redistributed lines that extend in multiple dimensions, the design accommodates higher I/O counts without reducing the minimum bond pitch, thus maintaining manufacturing precision while enhancing adaptability.
3Strength
If copper is used as soldering material to improve soldering characteristics, then adhesion to solder bumps improves, but wire bonding reliability deteriorates due to oxide layer formation
Solution Approach 1:
The pad is segmented into distinct regions where copper-rich composition is localized in the first pad region for solder bump adhesion, while the second pad region uses materials with lower oxide formation tendency for wire bonding. This spatial segmentation resolves the material property conflict.
Solution Approach 2:
A barrier layer or intermediate material is introduced between the copper layer and the wire bonding contact region to prevent oxide formation while allowing electrical connection. This intermediary protects the copper from oxidation in areas where wire bonding occurs, maintaining both soldering and bonding reliability.
4Reliability
If aluminum is used for wire bonding to improve bonding characteristics, then wire bonding reliability improves, but soldering quality deteriorates due to strong oxide layer formation
Solution Approach 1:
The pad structure is segmented to place aluminum-rich materials in the second pad region for wire bonding, while the first pad region uses materials with lower oxide content for soldering. This segmentation allows aluminum to provide reliable wire bonding without compromising soldering quality in the other region.
Solution Approach 2:
Aluminum material is locally applied only in regions where wire bonding occurs, with controlled thickness and composition. In soldering regions, the aluminum content is reduced or replaced with materials that form weaker oxide layers, ensuring high-quality solder joints while maintaining wire bonding reliability where aluminum is present.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and efficiency of semiconductor packages by preventing diffusion issues and ensuring uniform electrical connections, enabling higher I/O pin capacity and improved mechanical stability, thus addressing the limitations of existing techniques.
Implementation Method 1
A first barrier layer is disposed between the first external terminal connection pad and the redistributed line to prevent an ingredient included in the redistributed line from being diffused into the first external connection pad
Data Source
AI summary
Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.