Semiconductor Pad Segmentation for Defect-Tolerant Electrical Connections
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Solution Overview
Problem
Semiconductor devices face reliability issues due to defects in redistribution layers, which can lead to unstable electrical connections, affecting the reliability of both the semiconductor device and the semiconductor package.
Innovation Solution
A semiconductor device design featuring a semiconductor chip body with a passivation film and a redistribution layer that exposes a chip center pad region, a redistribution center pad region, and an edge pad region, where the top surfaces of the redistribution center pad region and chip center pad region are not on the same plane, enhancing electrical connection stability even when defects occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a redistribution layer is used to change pad positions, then pad placement convenience is improved, but reliability of electrical connection deteriorates due to potential defects in the redistribution layer
Solution Approach 1:
The pad structure is segmented into multiple regions: a first pad region directly connected to the chip pad, a second pad region connected to the first pad region through the redistribution layer, and a third pad region connected to the second pad region. This segmentation creates multiple independent electrical connection paths, so that if the redistribution layer has defects, the connection can still be maintained through alternative paths via the first and third pad regions.
Solution Approach 2:
The invention changes the topography parameter of the pad structure by creating non-coplanar surfaces. The first pad region has a top surface at a first level, the second pad region has a top surface at a second level, and the third pad region has a top surface at a third level. This multi-level structure allows for stable bonding interfaces while accommodating the redistribution layer in between, maintaining electrical connection reliability despite the presence of the redistribution layer.
2Adaptability or versatility
If pads are disposed in a specific region to ease circuit crowding, then circuit layout flexibility is improved, but connection stability deteriorates when defects occur in the redistribution layer
Solution Approach 1:
The pad structure is divided into multiple functional regions (first, second, and third pad regions) with different connectivity functions. The first pad region provides direct connection to the chip pad, the second pad region interfaces with the redistribution layer, and the third pad region provides alternative connection paths. This segmentation enables flexible circuit layout while maintaining connection stability through redundant pathways.
Solution Approach 2:
The invention prepares compensatory connection structures in advance by creating the first and third pad regions that can compensate for potential defects in the redistribution layer. These redundant connection paths are built into the structure beforehand, providing a cushion against connection failures and ensuring continued operation even when the redistribution layer has defects.
3Ease of manufacture
If a single-plane pad structure is used, then manufacturing simplicity is maintained, but bonding stability deteriorates
Solution Approach 1:
The invention transitions from a single-plane (2D) pad structure to a multi-level (3D) pad structure. The first, second, and third pad regions are positioned at different vertical levels, creating a stepped configuration. This dimensional change provides stable bonding surfaces at each level while accommodating the redistribution layer, improving bonding stability without significantly complicating the manufacturing process.
Data Source
AI summary
Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.