Semiconductor Pad Segmentation to Suppress Dicing Cracks
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Solution Overview
Problem
The increasing number of wiring layers in semiconductor wafers during the dicing process leads to a higher likelihood of crack formation, which can extend from the scribe line into the device formation area, affecting electronic circuit operation, especially when the scribe line width is narrowed.
Innovation Solution
A semiconductor device design with a scribe region at the outer periphery of the chip region, featuring a multi-layer wiring structure with via-plugs connecting conductive films across layers, and conductive patterns in the pad region that are strategically positioned to reduce the impact of ductility on the dicing blade, such as ring-shaped patterns or discrete dot patterns, to minimize crack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of wiring layers is increased, then the functionality and integration density of the semiconductor device is improved, but the likelihood of crack formation during dicing increases
Solution Approach 1:
The pad structure is segmented into multiple layers with via-plugs connecting conductive films between wiring layers. This segmentation distributes the mechanical stress across multiple discrete connection points rather than continuous pads, reducing crack propagation during dicing while maintaining the necessary electrical connectivity for increased wiring layer functionality.
Solution Approach 2:
The pad structure implements local quality by positioning via-plugs at specific locations (such as corners) rather than uniformly distributing pads across the entire pad region. This localized approach reduces the overall pad material in the scribe line area, minimizing ductility effects on the dicing blade while ensuring adequate electrical connection at critical points.
2Area of stationary object
If the scribe line width is narrowed, then the chip area is maximized, but cracks can more easily reach the area inside the seal ring and affect circuit operation
Solution Approach 1:
By segmenting the pad structure into multi-layer conductive films connected by via-plugs, the mechanical continuity that facilitates crack propagation is broken. The narrowed scribe line can be maintained while the segmented pad structure prevents cracks from traveling continuously from the scribe line to the seal ring area.
Solution Approach 2:
The pad structure transitions from a two-dimensional continuous pad to a three-dimensional multi-layer structure with via-plugs. This dimensional change allows the pads to maintain electrical functionality while reducing their footprint in the planar scribe line area, enabling narrower scribe lines without increasing crack risk to the seal ring.
3Reliability
If pads are formed in multiple wiring layers, then the electrical connectivity is improved, but the number of pads in scribe lines increases and crack formation becomes more likely
Solution Approach 1:
Multiple conductive films from different wiring layers are merged vertically through via-plugs to form integrated pad structures. This merging reduces the total number of discrete pads in the scribe line area while maintaining electrical connectivity across multiple wiring layers, thereby reducing crack formation risk.
Solution Approach 2:
The pad structure implements a nested configuration where conductive films from different wiring layers are nested vertically and connected through via-plugs. This nesting consolidates multiple electrical connection functions into a compact vertical structure, reducing the horizontal pad presence in scribe lines and minimizing crack generation during dicing.
Data Source
AI summary
A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.