3D Memory Stack Pad Formation via Selective Dielectric Etching
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Solution Overview
Problem
Current three-dimensional nonvolatile memory devices face challenges in improving operational reliability due to limitations in the integration of memory cells in multiple layers on a substrate, requiring enhanced manufacturing methods and structures to maintain data retention and performance.
Innovation Solution
A semiconductor device and manufacturing method involving a stack structure with a channel layer, gap fill layer composed of dielectric layers with different etching rates, and selective etching to form pads, which improves the uniformity and reliability of transistor overlap and threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are vertically stacked in multiple layers to improve integration density, then the degree of integration is improved, but manufacturing precision and structural stability deteriorate
Solution Approach 1:
The gap fill layer is divided into multiple dielectric layers with different etching rates (first dielectric layer, second dielectric layer, third dielectric layer). This segmentation allows selective removal of specific layers during manufacturing, enabling precise control of pad thickness and height while maintaining the overall vertical stack structure for high integration density.
Solution Approach 2:
Different etching rates are assigned to different dielectric layers through material selection. The first dielectric layer has a higher etching rate than the second, and the third dielectric layer has a higher etching rate than both first and second layers. This parameter variation enables selective etching processes to achieve precise dimensional control in the vertical stack structure.
2Reliability
If gap fill layer height is increased to improve transistor overlap, then transistor overlap is improved, but manufacturing complexity increases
Solution Approach 1:
The gap fill layer is segmented into multiple dielectric layers that can be selectively etched. This allows the pad thickness to be precisely controlled by removing specific layers, achieving the required transistor overlap without increasing overall manufacturing complexity.
Solution Approach 2:
The third dielectric layer acts as an intermediary with high etching selectivity. It can be selectively removed to expose the channel layer and control the pad thickness, serving as a mediator that enables precise dimensional control without affecting other parts of the structure.
3Manufacturing precision
If selective etching is used to control pad thickness, then pad thickness uniformity is improved, but process difficulty increases
Solution Approach 1:
Different etching rates are assigned to different dielectric layers through material selection. The first dielectric layer has a higher etching rate than the second, and the third dielectric layer has a higher etching rate than both first and second layers. This parameter variation enables selective etching processes to achieve precise dimensional control.
Solution Approach 2:
The third dielectric layer acts as an intermediary with high etching selectivity. It can be selectively removed to expose the channel layer and control the pad thickness, serving as a mediator that enables precise dimensional control without affecting other parts of the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the stability and reliability of semiconductor devices by allowing for more precise control of the gap fill layer height and pad thickness, leading to improved transistor overlap and uniform threshold voltage distribution, thereby increasing the operational reliability of three-dimensional nonvolatile memory devices.
Implementation Method 1
forming an opening by selectively etching the first dielectric layer; selectively etching the second dielectric layer exposed through the opening
Data Source
AI summary
In a method of manufacturing a semiconductor device, the method includes: forming a stack structure; forming a channel layer penetrating the stack structure; forming a first dielectric layer in the channel layer; forming a second dielectric layer in the first dielectric layer; forming an opening by selectively etching the first dielectric layer; selectively etching the second dielectric layer exposed through the opening; and forming a pad in the opening.