Semiconductor Signal Path Swapping for Shared Pad Calibration

The patent merges the calibration functions of multiple semiconductor chips by enabling them to share a common set of pads through signal path swapping. Instead of requiring separate dedicated pads for each chip's calibration operation, the chips can sequentially or simultaneously access the same pads by dynamically reconfiguring the signal paths within each chip, thus reducing the total number of pads required while maintaining independent calibration capability for each chip.

The patent introduces dynamic signal path switching within each semiconductor chip using swapping circuits that can reconfigure the connection between internal calibration circuits and external pads. This dynamic reconfiguration allows the same physical pads to serve multiple calibration functions across different chips, transforming a static pad allocation into a flexible, time-multiplexed resource sharing arrangement.

Instead of using crossed wire bondings to achieve signal path swapping between chips, the patent inverts the approach by implementing swapping circuits within each chip that can reconfigure which pad connects to which internal circuit. This eliminates the need for complex crossed wire bondings while achieving the same functional outcome of flexible signal routing.

The patent introduces swapping circuits as intermediary components within each semiconductor chip that mediate the connection between pads and internal circuits. These swapping circuits act as controllable switches or multiplexers that dynamically route signals between different pads and internal calibration circuits, replacing the need for fixed crossed wire bondings and simplifying the manufacturing process.

The patent ensures that each semiconductor chip maintains high signal integrity during calibration by providing dedicated, isolated signal paths within the chip's internal swapping circuitry. Even though multiple chips share external pads, each chip's internal calibration signals are routed through dedicated traces and switching elements that prevent interference from other chips, thus maintaining local signal quality despite global resource sharing.

The patent implements control logic that manages the timing and sequencing of calibration operations across multiple chips sharing common pads. By coordinating when each chip performs calibration and when the swapping circuits connect to the shared pads, the system prevents signal conflicts and interference, ensuring that signal integrity is maintained even with a reduced number of pads.