Semiconductor Pad-Via Layout for Thermal Stress Cracking
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Solution Overview
Problem
The ever-decreasing geometry size of semiconductor integrated circuits (ICs) leads to physical stress issues due to temperature changes, causing problems such as peeling or cracking in metal pads and passivation layers, which are exacerbated by the reduction in size of conventional metal pads and passivation layers.
Innovation Solution
A novel semiconductor structure incorporating well-designed vias that provide support for metal pads, with specific dimensions and configurations to reduce stress and prevent cracking, including elongated vias aligned symmetrically with pads and formed in a single process with the pads, ensuring increased contact areas and reduced contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of metal pads and passivation layers is reduced to achieve smaller geometry sizes, then the functional density increases, but physical stress and cracking in these layers worsen
Solution Approach 1:
The patent divides the metal pad structure into multiple segments by introducing via structures that split the pad into distinct regions. These segmented via structures are distributed across the pad area, creating a modular configuration that reduces stress concentration in any single region while maintaining overall pad functionality and electrical connectivity.
Solution Approach 2:
The patent applies local quality by creating regions of different via density and configuration within the metal pad structure. Certain areas have higher via concentrations or different via dimensional characteristics tailored to local stress patterns, allowing optimized stress distribution without compromising the overall pad performance or electrical characteristics.
2Productivity
If conventional metal pads and passivation layers are reduced in size, then device integration increases, but cracking and delamination are exacerbated
Solution Approach 1:
The patent implements beforehand cushioning by pre-configuring via structures within the metal pad design before fabrication. These via structures act as stress-absorbing elements that cushion against thermal expansion and contraction forces, preventing cracking and delamination from occurring in the first place during temperature cycling and device operation.
Solution Approach 2:
The patent employs composite material principles by combining multiple material layers with different mechanical and thermal properties in the pad structure. The via structures utilize materials with appropriate thermal expansion coefficients that bridge between the metal pad and underlying substrates, creating a composite system that accommodates thermal stress while maintaining structural integrity.
Data Source
AI summary
A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.