Semiconductor Page Buffer Contact Placement for BVDSS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Highly integrated semiconductor memory devices face reliability issues due to decreased drain-source breakdown voltage (BVDSS) of high-voltage transistors in page buffers, which affects erase operations and overall device reliability, especially when reducing the number of manufacturing steps and wiring layers is necessary for cost and efficiency.
Innovation Solution
The placement of contacts coupled to junction regions in semiconductor memory devices is optimized, with those receiving erase voltage positioned at the center of the active region and those not receiving it positioned at the edge, maintaining high BVDSS while reducing the number of wiring layers, thereby supporting high-voltage transistor functionality and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the number of wiring layers is reduced to improve manufacturing efficiency and reduce costs, then manufacturing complexity decreases, but the drain-source breakdown voltage (BVDSS) of high-voltage transistors decreases, leading to reliability issues
Solution Approach 1:
The patent applies local quality by differentiating the contact positions based on their functional requirements. Contacts for junction regions receiving erase voltage are positioned at the center of the active region, while contacts for junction regions not receiving erase voltage are positioned at the edge. This localized differentiation maintains high BVDSS for high-voltage transistors while enabling reduced wiring layer complexity for manufacturing efficiency.
2Productivity
If high integration is implemented to reduce manufacturing cost, then device density increases, but structural changes are required that decrease the reliability of nonvolatile memory devices
Solution Approach 1:
The patent implements local quality by positioning contacts at different locations within the active region based on their specific functional requirements. This allows the device to achieve high integration and density while maintaining reliable erase operations and overall device performance through optimized local contact configurations.
Solution Approach 2:
The patent utilizes the spatial dimension within the active region by positioning contacts at different locations (center vs. edge) in the planar view. This dimensional optimization allows multiple contacts to be accommodated within the same active region without increasing the number of wiring layers, thereby achieving high integration while maintaining reliability.
3Reliability
If contacts are positioned to optimize erase voltage loading, then erase operation reliability improves, but device structure becomes more complex
Solution Approach 1:
The patent applies local quality by assigning specific positions to contacts based on their functional role. Contacts for junction regions receiving erase voltage are positioned at the center of the active region to optimize erase operation reliability, while other contacts are positioned at the edge. This localized optimization achieves reliable erase operations without requiring complex overall device structures.
Data Source
AI summary
A semiconductor memory device includes at least two transistors, each including a gate that traverses, in a first direction, an active region of a first substrate defined by an isolation layer, and junction regions disposed in the active region on opposite sides of the gate, and coupled to a memory cell array through a bit line; and a plurality of contacts, coupled respectively to the junction regions, that pass through a dielectric layer that covers the transistor. Among the plurality of contacts, a contact coupled to a junction region to which an erase voltage is loaded is disposed at a center portion of the active region in the first direction, and a contact coupled to a junction region to which the erase voltage is not loaded is disposed at an edge portion of the active region in the first direction.