Semiconductor Device Page Buffer Multi-Bit Read Voltage Sequencing
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Solution Overview
Problem
Nonvolatile memory devices face challenges in improving data processing speed due to lengthy verification, program, and read operations, particularly in handling multi-bit data storage and retrieval efficiently.
Innovation Solution
A semiconductor device and method that utilize a page buffer and sequential application of read voltages with varying levels to selected word lines while maintaining unselected lines at a pass voltage, enabling concurrent data sensing and storage in latches, followed by outputting multi-bit data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If nonvolatile memory device performs traditional read operation with sequential verification, then data storage reliability is ensured, but data processing speed deteriorates due to lengthy verification time
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines and setting word lines to pass voltage before the actual read operation begins. This preparatory setup eliminates the need for time-consuming verification steps during the read operation, as the memory device is already in the optimal state for immediate data retrieval, thus reducing verification time while maintaining read accuracy
Solution Approach 2:
The patent implements continuity of useful action by maintaining word lines at pass voltage throughout the read operation and using sequential read voltages on the selected word line without interrupting the sensing process. This continuous operation allows multi-bit data to be read sequentially from the same memory cell without requiring repeated verification cycles, thereby reducing total verification time while ensuring data reliability
2Quantity of substance
If nonvolatile memory device increases data storage capacity with multi-bit cells, then storage density is improved, but read operation complexity increases due to multiple voltage levels required
Solution Approach 1:
The patent applies segmentation by dividing the read operation into distinct sequential steps, each targeting a specific bit of multi-bit data stored in the memory cell. By applying different read voltages to the selected word line in sequence and sensing each bit separately through the page buffer, the complex task of reading multi-bit data is broken down into manageable segments, reducing operational complexity while maintaining high storage capacity
Solution Approach 2:
The patent utilizes parameter changes by varying the voltage level applied to the selected word line according to the specific bit being read. Different voltage levels (e.g., 0V, Vr1, Vr2, Vr3) are applied sequentially to sense different bits of multi-bit data, enabling the memory device to retrieve multiple bits from a single cell through controlled parameter variation rather than complex circuitry
Data Source
AI summary
A semiconductor device may include at least one memory string that is connected between a bit line and a source line and includes a plurality of memory cells connected to a plurality of word lines, and a page buffer connected to the bit line and configured to sense data stored in the plurality of memory cells. Multi-bit data stored in a selected memory cell of the plurality of memory cells may be consecutively output by sequentially providing a selected word line of the plurality of word lines with read voltages having different levels in a state in which unselected word lines of the plurality of word lines are provided with a pass voltage.