Semiconductor Junctions Using Pre-Amorphization Implantation
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Solution Overview
Problem
As semiconductor devices miniaturize, achieving optimal punch-through voltage and breakdown voltage while maintaining resistance values in source and drain regions becomes increasingly challenging due to reduced voltage correlations, affecting device reliability.
Innovation Solution
A semiconductor device and fabrication method involving a substrate with stack layers, doped regions, and a pre-amorphization implantation (PAI) region, where the second dopant with a faster diffusion rate and higher thermal activation is surrounded by a first dopant with slower diffusion, using ion implantation processes to optimize junctions and prevent dopant diffusion into the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices are miniaturized to improve integration, then device size decreases, but punch-through voltage and breakdown voltage are reduced
Solution Approach 1:
The patent applies local quality by creating distinct doped regions with different dopant concentrations and types within the source/drain structure. Specifically, a first doped region with a first dopant concentration is formed adjacent to the channel, and a second doped region with a second dopant concentration is formed in the substrate, where the dopant concentrations are different. This local differentiation allows optimization of electrical properties at different locations to maintain voltage characteristics despite device miniaturization.
Solution Approach 2:
The patent employs preliminary action through the pre-amorphization implantation (PAI) process. A PAI region is formed in the first doped region before the actual dopant implantation. This pre-amorphization layer controls the diffusion and distribution of subsequent dopants, ensuring precise dopant placement and concentration profiles are achieved even in miniaturized devices, thereby maintaining reliable voltage characteristics.
2Reliability
If dopant diffusion rate is increased to improve thermal activation, then dopant distribution improves, but dopant diffuses into substrate uncontrollably
Solution Approach 1:
The pre-amorphization implantation (PAI) region is formed before dopant implantation to control subsequent dopant diffusion. The PAI region creates a controlled amorphous structure that guides dopant distribution, allowing high thermal activation and diffusion rates during annealing while preventing uncontrolled dopant spread into the substrate. The PAI region acts as a diffusion barrier and template for precise dopant placement.
Solution Approach 2:
The patent utilizes parameter changes by varying the dopant concentration between different regions (first dopant concentration in the first doped region, second dopant concentration in the second doped region) and using different dopant types with different diffusion characteristics. This allows optimization of thermal activation in regions where it is needed while maintaining manufacturing precision through controlled concentration gradients and selective doping schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances punch-through and breakdown voltages by optimizing the junctions of the semiconductor device, maintaining resistance values and improving device reliability.
Implementation Method 1
the highly-active second dopant does not easily diffuse into the substrate because of the PAI region
Implementation Method 2
A first doped region of a second conductivity type is formed in the substrate between the stack layers, wherein the first doped region has a first dopant. A pre-amorphization implantation process is performed to form a PAI region in the first doped region. A first spacer is formed respectively on a sidewall of each of the stack layers. The first spacer is used as a mask to implant a second dopant
Data Source
AI summary
Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer and a conductive layer. The dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. First doped region of a second conductivity type has a first dopant and is disposed in the substrate between the stack layers. A pre-amorphization implantation (PAI) region is disposed in the first doped region. A second doped region of the second conductivity type has a second dopant and is disposed in the PAI region. The first conductivity type is different from the second conductivity type. A diffusion rate of the second dopant is faster than a diffusion rate of the first dopant, and a thermal activation of the second dopant is higher than that of the first dopant.