Semiconductor Paired Marks for Stress-Resilient Alignment
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Solution Overview
Problem
The position of misalignment marks in semiconductor devices can be displaced due to stress in the layers, leading to inaccurate inspection of misalignment between hierarchical layers during the manufacturing process.
Innovation Solution
Paired marks are arranged in the kerf region on the same hierarchical layer, with one mark on the upper layer and the other on the lower layer, allowing for accurate alignment inspection by determining positions where stress distribution is minimal, thereby minimizing the impact of stress-induced misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If misalignment marks are used for inspecting misalignment between hierarchical layers, then alignment inspection can be performed, but the position of the misalignment mark may be displaced due to stress in each layer, leading to inaccurate inspection
Solution Approach 1:
A dummy pattern is introduced as an intermediary reference object in the same hierarchical layer as the misalignment marks. This dummy pattern serves as a stable reference that is not affected by stress-induced displacement, allowing accurate measurement of the misalignment mark's position relative to a fixed point in the layer structure.
Solution Approach 2:
The reference frame for alignment inspection is changed from using fixed structural features that may be stress-sensitive to using a dummy pattern that is specifically designed to be stress-insensitive. This parameter change in the reference system allows accurate alignment measurement despite stress-induced displacements in the hierarchical layers.
2Measurement precision
If paired marks are arranged in the kerf region on the same hierarchical layer, then accurate alignment inspection can be achieved, but the device complexity increases due to additional mark arrangement
Solution Approach 1:
The dummy pattern serves multiple functions: it acts as a reference for alignment inspection, compensates for stress-induced displacements, and provides a stable reference frame for measuring misalignment between hierarchical layers. This multi-functionality reduces the need for additional complex reference structures.
Solution Approach 2:
A simplified dummy pattern is created as a copy or replica of the hierarchical layer structure, specifically designed to mirror the layer's position without being affected by stress. This copied reference structure allows accurate alignment measurement without adding significant complexity to the device.
Data Source
AI summary
A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.