Semiconductor Device Parallel Lead Terminals Inductance Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing wiring inductances, leading to increased size and weakened mechanical strength due to misaligned metal foil pieces and external lead terminals, which results in higher surge voltages during switching operations.
Innovation Solution
A semiconductor device design featuring an insulating substrate with conductive patterns and conductive pins, where positive-electrode and negative-electrode external lead terminals are disposed adjacent to each other in parallel, and conductive pins are fixed to semiconductor elements and patterns, reducing wiring inductances and device size by opposing metal foil pieces on the printed circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If metal foil pieces are disposed on the printed circuit board to reduce wiring inductances, then wiring inductances are reduced, but the device size increases due to misalignment with semiconductor chips
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Metal foil pieces are disposed on both the front and rear surfaces of the printed circuit board, utilizing the third dimension (depth/layering) to reduce wiring inductances without increasing the device's footprint area.
Solution Approach 2:
The patent employs asymmetric positioning of metal foil pieces on the front and rear surfaces of the printed circuit board. The foil pieces are strategically positioned to align with semiconductor chip locations, creating an asymmetric but optimized current path that reduces inductances while maintaining compact dimensions.
2Ease of operation
If external lead terminals are connected to the printed circuit board, then electrical connections are established, but the mechanical strengths of connecting parts are weakened
Solution Approach 1:
The patent merges the electrical connection function with the structural support function by integrating external lead terminals directly into the printed circuit board assembly. The metal foil pieces and terminals are combined with the board structure to create a unified component that provides both electrical connectivity and mechanical strength.
3Object-affected harmful factors
If external lead terminals are disposed in parallel to reduce wiring inductances, then wiring inductances are reduced, but the device complexity increases
Solution Approach 1:
The printed circuit board in the patent serves multiple functions simultaneously: it provides mechanical support, establishes electrical connections, reduces wiring inductances through parallel terminal arrangement, and positions metal foil pieces for optimal current paths. This multi-functionality reduces overall device complexity despite the parallel terminal configuration.
Data Source
Figure 1(a)~1(b)
Figure 2(a)~2(b)
Figure 3
AI summary
Semiconductor chips 9 to 12 are disposed on an insulating substrate with conductive patterns 1, and a printed circuit board with metal pins 13 is disposed above the insulating substrate with conductive patterns 1, with the semiconductor chips 9 to 12 therebetween. A plurality of external lead terminals 21, 22, 23 are fixed to the insulating substrate with conductive patterns 1, with the plurality of external lead terminals 21, 22 disposed adjacent to each other in parallel. Furthermore, metal foil pieces 15, 16, formed on front and rear surfaces of the printed circuit board with metal pins 13 respectively so as to oppose each other, are disposed above the semiconductor chips 9 to 12.