Semiconductor Terminal Layout With Parallel Plates for Low Inductance
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Solution Overview
Problem
Conventional semiconductor devices with complex electrical circuits face increased size due to high inductance between high and low potential terminals, which is not effectively addressed by existing techniques.
Innovation Solution
The semiconductor device design includes a circuit pattern on a low potential side and an adjacent high potential side on an insulating substrate, with terminals forming parallel flat plates to reduce the length between them, thereby decreasing inductance while allowing for downsizing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the circuit wiring is improved to downsize the semiconductor device, then the device size is reduced, but the inductance between high and low potential terminals increases
Solution Approach 1:
The patent transitions from planar parallel terminals to three-dimensional stacked terminals with vertical connection portions extending in the thickness direction. This dimensional change allows the terminals to be positioned adjacent to each other in the planar view (reducing device size) while maintaining short current paths through the vertical extensions (controlling inductance).
Solution Approach 2:
The connection portions are embedded within the insulating substrate, with terminal electrodes positioned adjacent to each other on the surface while their connection portions extend vertically through the substrate thickness. This nesting approach allows compact planar arrangement while maintaining effective electrical connection paths.
2Adaptability or versatility
If multiple semiconductor chips are mounted on an insulating substrate to form a complex electrical circuit, then the circuit functionality is enhanced, but the wiring area and device size increase
Solution Approach 1:
By utilizing the thickness direction for vertical connection portions, the patent enables complex multi-chip circuits to be implemented with compact planar footprint. The vertical extensions allow multiple chips to be electrically connected through the substrate without requiring large lateral wiring areas.
Solution Approach 2:
Multiple semiconductor chips are mounted on the insulating substrate with their respective terminals connected through the vertical connection portions embedded in the substrate. This merging approach integrates multiple chips into a compact three-dimensional configuration, reducing overall device size while maintaining circuit functionality.
Data Source
AI summary
An object is to provide a semiconductor device capable of reducing inductance between a high potential terminal and a low potential terminal while achieving downsizing of the semiconductor device. A semiconductor device includes: the insulating substrate; the circuit pattern including a low potential circuit pattern and a high potential circuit pattern provided on a region adjacent to the low potential circuit pattern; a plurality of semiconductor chips mounted on the circuit pattern; a low potential terminal having one end portion connected to the low potential circuit pattern; and a high potential terminal having one end portion connected to the high potential circuit pattern, wherein the high potential terminal and the low potential terminal include electrode parts and constituting parallel flat plates vertically disposed in parallel to each other and extending on a side of the low potential circuit pattern and electrode parts and protruding from the insulating substrate.