Semiconductor Apparatus Parallel PN-Layer Field Plate
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Solution Overview
Problem
Conventional semiconductor apparatuses face challenges in maintaining robustness against surface charges, leading to fluctuations in breakdown voltage over time, particularly due to the trade-off between on-resistance and breakdown voltage, and the lack of effective peripheral structures to manage electric fields.
Innovation Solution
A semiconductor apparatus design featuring a first parallel pn-layer between an active region and a low-resistance layer, a second parallel pn-layer with a narrower repetition pitch in the peripheral region, and third regions of varying conductivity to manage electric fields and charge imbalances, including a conductive layer connected to the outermost third region and a termination of the peripheral region to collect charges and stabilize the electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the n−-drift layer is thinned to reduce on-resistance, then on-resistance decreases, but breakdown voltage decreases due to smaller depletion layer expansion
Solution Approach 1:
The drift layer is segmented into multiple thin drift layers separated by intrinsic or low-doped semiconductor layers. This segmentation allows the total thickness to be reduced for lower on-resistance while the multiple interfaces enhance depletion layer expansion for maintained breakdown voltage
Solution Approach 2:
The patent uses composite structure combining n-type doped layers with intrinsic or low-doped layers to create a multi-layer drift region that achieves both low resistance and high breakdown voltage through the synergistic effect of the different layers
2Reliability
If a peripheral structure is added to maintain high breakdown voltage, then breakdown voltage is maintained, but device complexity increases
Solution Approach 1:
The segmented drift layer structure serves dual functions: it reduces on-resistance through thin layers while simultaneously maintaining breakdown voltage through multiple depletion interfaces, eliminating the need for separate peripheral structures
Solution Approach 2:
The patent merges the functions of the drift layer and the depletion layer by creating multiple interfaces within the drift region itself, combining the benefits of thin layers and extensive depletion expansion in a single integrated structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the robustness against surface charges by relaxing high electric fields near the active region and preventing depletion layer expansion, thereby maintaining high breakdown voltage and reducing voltage fluctuations caused by positive and negative charges.
Implementation Method 1
a depletion layer expands laterally from vertically extending pn-junctions of the parallel pn-structure to be depleted of carrier in the entire drift layer, which achieves high breakdown voltage
Implementation Method 2
a second parallel pn-layer being composed of second regions of the first conductivity alternately arranged with second regions of the second conductivity, at a repetition pitch narrower than a repetition pitch of the first regions
Data Source
AI summary
A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n+-drain region. A peripheral region is provided with a second parallel pn-layer, which has a repetition pitch narrower than the repetition pitch of the first parallel pn-layer. An n−-surface region is formed between the second parallel pn-layer and a first main surface. On the first main surface side of the n−-surface region, a plurality of p-guard ring regions are formed to be separated from each other. A field plate electrode is connected electrically to the outermost p-guard ring region among the p-guard ring regions. A channel stopper electrode is connected electrically to an outermost peripheral p-region of the peripheral region.