Semiconductor Parameter Setting Using Neural Networks to Minimize PDP

The patent performs preliminary actions by collecting manufacturing parameter data and electrical performance data from previous wafers, and training a neural network model in advance to establish a predictive relationship between manufacturing parameters and electrical performance. This pre-trained model can then quickly predict optimal parameters without requiring repeated actual wafer manufacturing and feedback loops, thus resolving the contradiction between manufacturing precision and time loss.

The patent creates a virtual copy of the manufacturing process by training a neural network model that replicates the relationship between manufacturing parameters and electrical performance based on historical data. This digital twin or virtual model allows for prediction and optimization without requiring repeated physical wafer manufacturing, thereby maintaining manufacturing precision while significantly reducing the time and cost associated with physical experimentation and feedback loops.

The patent applies parameter changes by taking the logarithm of manufacturing parameters before inputting them to the neural network model. This transformation simplifies the input data distribution and improves the convergence and prediction accuracy of the model. Additionally, the model is trained to predict specific electrical performance parameters (power and delay) directly, which are critical for semiconductor optimization, thereby achieving high productivity through efficient parameter prediction while managing model complexity through appropriate data transformation.