Semiconductor Device Parasitic Capacitance Reduction
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Solution Overview
Problem
Miniaturization of semiconductor devices leads to reduced storage capacity and increased parasitic capacitance, making it difficult to effectively hold and recover data.
Innovation Solution
A semiconductor device with a novel structure that includes a plurality of memories, each comprising a volatile and a nonvolatile memory portion, where the transistors are designed with an oxide semiconductor layer and a capacitor configuration that reduces parasitic capacitance by separating the gate electrode layer and memory cell wiring layer into different layers, allowing for increased on-state current without complicating the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If elements are miniaturized to increase storage capacity per unit area, then the area of capacitor decreases, but parasitic capacitance becomes significant and storage capacity for holding data decreases
Solution Approach 1:
The patent separates the gate electrode layer and memory cell wiring layer into different layers, utilizing vertical layering to reduce parasitic capacitance between adjacent conductors. This dimensional separation allows the capacitor to maintain sufficient storage capacity even with reduced area, as the parasitic capacitance effect is minimized through spatial isolation in the vertical dimension.
2Area of stationary object
If transistor size is reduced to increase storage capacity per unit area, then on-state current decreases, but data holding and recovery becomes difficult
Solution Approach 1:
The patent employs an oxide semiconductor layer as the semiconductor material in the transistor, which provides high mobility and high on-state current even in miniaturized structures. This composite material approach maintains sufficient on-state current for data holding and recovery operations while keeping the transistor area reduced for increased storage capacity.
3Ease of manufacture
If gate electrode layer and memory cell wiring layer are in the same layer, then manufacturing is simpler, but parasitic capacitance increases
Solution Approach 1:
The patent implements a multi-layer structure where the gate electrode layer and memory cell wiring layer are positioned in different vertical layers. This dimensional separation effectively reduces parasitic capacitance between these conductors while maintaining manufacturing feasibility through standard multi-layer fabrication processes.
Data Source
AI summary
A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.