Semiconductor Structure Parasitic Capacitance Reduction
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Solution Overview
Problem
In RFID and remote sensor systems, parasitic circuit components such as resistors and capacitors can negatively impact performance, especially in high-frequency applications, and existing methods to minimize their effects are either costly or difficult to implement in compact IC architectures.
Innovation Solution
A semiconductor structure is designed with electrically conductive layers forming a capacitor underneath the pad, incorporating Schottky diodes with negligible parasitic capacitance, and a multistage rectifier circuit arrangement that reduces parasitic influences by placing stages under the pad, utilizing a highly doped zone and metallic properties in junction regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large resistors with low quality factor are used to reduce parasitic effects, then parasitic compensation is improved, but space requirements increase and cost increases
Solution Approach 1:
The patent extracts the parasitic compensation function from separate lateral resistor structures and integrates it into the vertical substrate zone directly beneath the pad. This eliminates the need for additional lateral space while maintaining the parasitic reduction effect through the highly doped substrate region.
Solution Approach 2:
The patent transitions from lateral parasitic compensation structures to a vertical implementation by creating a highly doped substrate zone directly beneath the pad. This dimensional shift allows parasitic compensation to be achieved within the substrate depth rather than requiring lateral expansion.
2Object-affected harmful factors
If the pad area is reduced to minimize parasitic capacitance, then parasitic effects are reduced, but the quality factor improvement is limited
Solution Approach 1:
The patent changes the doping parameter of the substrate zone beneath the pad, creating a highly doped region with different electrical characteristics. This parameter modification reduces parasitic capacitance effects while maintaining or improving quality factor without requiring pad area reduction.
3Reliability
If complex rectifier circuits are used to improve HF performance, then rectifier efficiency is improved, but device complexity increases
Solution Approach 1:
The patent converts the typically harmful parasitic substrate capacitance into a beneficial element by creating a highly doped substrate zone that forms an intentional capacitor. This structure, which could be seen as a parasitic element, is instead utilized to improve rectifier efficiency and HF performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces parasitic capacitance and enhances the quality factor of the input circuit, leading to improved rectifier efficiency and compatibility with modern IC assembly methods like flip-chip technology.
Implementation Method 1
a first zone is arranged essentially completely underneath the first and second electrically conductive layers... the pad accordingly includes a capacitor that is formed by the two electrically conductive layers
Implementation Method 2
such transponders or remote sensors contain rectifier circuits which take energy that is transported by an HF carrier wave... and convert the carrier wave into a DC supply voltage
Data Source
AI summary
A semiconductor structure, for improving rectifier efficiency in passive backscatter transponders or backscatter remote sensors for use in high-frequency electromagnetic fields, is provided. The semiconductor structure has a dielectric layer on whose upper side is arranged a first electrically conductive layer, and a second electrically conductive layer that is spaced apart from the first electrically conductive layer and is arranged essentially below the first electrically conductive layer and is at least partially embedded in the dielectric layer. The dielectric layer has its lower side arranged on a semiconductor substrate of a first conductivity type within which is formed a more highly doped first zone of the first conductivity type which surrounds an even more highly doped second zone of the first conductivity type connected to a reference voltage. Whereby, the first zone can be arranged essentially completely under the first and second electrically conductive layers. In this way, interfering effects of parasitic circuit components can be reduced.