Semiconductor Integrated Circuit Parasitic Current Suppression
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Solution Overview
Problem
Existing semiconductor integrated circuits face reliability issues due to noise immunity challenges, particularly in high-voltage ICs where parasitic elements can cause operation errors and failures, especially in the vertical direction of the substrate where a large current flows.
Innovation Solution
The integration of a current suppression layer of the first conductivity type in the lower part of the semiconductor substrate below the first well region, separated from the well region, and an isolation region of the second conductivity type in the upper part of the substrate, with a reference potential applied to the isolation region, helps suppress the operation of parasitic elements by creating a potential barrier and reducing current amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional high voltage IC structure is used, then the device can perform power conversion functions, but parasitic elements generate large currents that cause operation errors and reduce reliability
Solution Approach 1:
An n-type current suppression layer is introduced as an intermediary element between the p-type semiconductor substrate and the n-type well region. This layer acts as a mediator to suppress the operation of parasitic p-n-p bipolar transistors by reducing current amplification in the vertical direction, thereby reducing harmful currents generated by parasitic elements without affecting the normal operation of the high voltage IC
Solution Approach 2:
The current suppression layer is selectively positioned in specific regions where parasitic elements are most problematic - specifically in the vertical direction below well regions containing high-side circuit formation regions. This localized approach targets the harmful current paths without interfering with the overall power conversion function of the device
2Power
If the area of parasitic elements is increased in the vertical direction, then more current can be handled, but the current amplification of parasitic elements increases causing operation failures
Solution Approach 1:
The n-type current suppression layer serves as an intermediary that disrupts the current amplification process of parasitic p-n-p bipolar transistors. By positioning this layer between the substrate and well regions, it reduces the beta value (current amplification factor) of parasitic elements, allowing the device to handle high currents without the parasitic elements amplifying these currents to failure levels
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the operation of parasitic p-n-p bipolar transistors, preventing operation errors and failures by reducing current flow through the parasitic elements, thereby enhancing the reliability of the semiconductor integrated circuits.
Implementation Method 1
creating a potential barrier and reducing current amplification
Implementation Method 2
reducing current flow through the parasitic elements
Data Source
AI summary
A semiconductor integrated circuit includes a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper part of the first well region; a current suppression layer of the first conductivity type provided in a lower part of the semiconductor substrate immediately below the first well region, separated from the first well region; and an isolation region of the second conductivity type provided in an upper part of the semiconductor substrate, separated from the first well region, a reference potential being applied to the isolation region. The semiconductor substrate is the second conductivity type.