Semiconductor Device Parasitic Transistor Suppression
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Solution Overview
Problem
The operation of parasitic transistors in semiconductor devices with voltage sense structures leads to reduced accuracy in temperature measurement and potential thermal damage due to increased current flow.
Innovation Solution
A semiconductor device structure is designed with a low lifetime region having a higher defect density or heavy metal diffusion under the second impurity region, and a gate electrode is placed between the semiconductor layer and the first semiconductor region with an insulation film, to suppress parasitic transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a voltage sense structure with p type impurity region and n type semiconductor region is formed, then temperature measurement capability is achieved, but parasitic NPN transistor operation occurs causing reduced measurement accuracy and thermal damage
Solution Approach 1:
The patent introduces a low lifetime region with specific properties (higher defect density or heavy metal diffusion) localized under the second impurity region. This creates a non-uniform structure where the low lifetime region specifically suppresses parasitic transistor operation by reducing carrier lifetime, while other regions maintain their original functions for voltage sensing and temperature measurement.
Solution Approach 2:
The patent changes the carrier lifetime parameter in the second impurity region by introducing defects through electron beam irradiation, proton irradiation, helium irradiation, or heavy metal diffusion. This parameter change (reducing lifetime) specifically targets the parasitic transistor current suppression while preserving the voltage sense structure's measurement capability.
2Reliability
If sense electrodes are connected to upper surfaces of p type impurity region and n type semiconductor region for voltage sensing, then temperature measurement is enabled, but current flow through parasitic transistor increases causing thermal damage
Solution Approach 1:
The low lifetime region is localized under the second impurity region to specifically intercept and suppress parasitic transistor current flow. This local modification reduces the harmful current without affecting the overall device structure or the voltage sensing function, thereby improving device safety against thermal damage.
Solution Approach 2:
The patent intentionally introduces defects or heavy metals that would normally be considered harmful (reducing material quality) but converts them into a beneficial low lifetime region that suppresses parasitic transistor operation. This transforms potential harm into a protective mechanism against excessive current and thermal damage.
3Object-generated harmful factors
If a low lifetime region with higher defect density or heavy metal diffusion is introduced under the second impurity region, then parasitic transistor operation is suppressed, but device structure complexity increases
Solution Approach 1:
The low lifetime region is formed in advance during the manufacturing process through electron beam irradiation, proton irradiation, helium irradiation, or heavy metal diffusion before final device assembly. This preliminary action integrates the parasitic suppression function into the base structure without requiring additional complex components or post-processing steps.
Solution Approach 2:
Instead of adding complex structural elements, the patent suppresses parasitic transistors by changing the physical parameters (carrier lifetime) of the existing second impurity region through controlled defect introduction or heavy metal diffusion. This parameter-based approach is simpler than structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the operation of parasitic transistors, thereby enhancing the accuracy of temperature measurement and preventing thermal damage by minimizing current flow.
Implementation Method 1
the second impurity region including a low lifetime region at least under the second semiconductor region, the low lifetime region being a region having a defect density higher than that in the surface layer of the second impurity region or a region in which a heavy metal is diffused
Implementation Method 2
applying electron beam irradiation, proton irradiation, or helium irradiation to at least a bottom portion of the second impurity region
Implementation Method 3
applying electron beam irradiation, proton irradiation, or helium irradiation to at least a bottom portion of the second impurity region
Implementation Method 4
applying electron beam irradiation, proton irradiation, or helium irradiation to at least a bottom portion of the second impurity region
Implementation Method 5
a gate electrode provided on the upper surface of the first impurity region lying between the semiconductor layer and the first semiconductor region, with an insulation film therebetween
Data Source
AI summary
There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.