Semiconductor Circuit Design Using Parasitic-Sensitive Net Analysis
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Solution Overview
Problem
Existing semiconductor integrated circuit designs face challenges in efficiently identifying and mitigating the impact of parasitic elements on circuit characteristics, which affect performance and efficiency.
Innovation Solution
A method and system for designing semiconductor integrated circuits that analyze and simulate various combinations of parasitic elements to identify high-sensitivity nets and wiring layers, allowing for targeted adjustments to reduce their influence on circuit characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If comprehensive circuit simulation including all parasitic elements is performed to accurately evaluate circuit characteristics, then measurement precision is improved, but loss of time increases due to repetitive simulations and layout corrections
Solution Approach 1:
The patent segments the comprehensive circuit simulation into multiple stages: initial simulation with all parasitic elements to identify critical nets, followed by focused simulation only on those critical nets. This segmentation reduces the total simulation scope and time while maintaining evaluation accuracy for the most impactful elements.
Solution Approach 2:
The patent applies local quality by concentrating detailed simulation resources on critical nets that have the most significant impact on circuit characteristics, while using simplified or omitted simulation for non-critical nets. This selective approach optimizes the balance between measurement precision and time consumption.
2Reliability
If comprehensive simulation with all parasitic elements is conducted to ensure reliability, then reliability is improved, but productivity decreases due to the need for repetitive layout corrections and simulations
Solution Approach 1:
The patent performs preliminary simulation to identify critical nets before final layout optimization. By determining which nets are most sensitive to parasitic elements in advance, the design process can focus efforts on the most critical areas, improving both reliability of evaluation and productivity through reduced iterative corrections.
Solution Approach 2:
The patent applies partial action by conducting detailed simulation only for critical nets rather than all nets. This partial approach maintains sufficient reliability for the most important circuit characteristics while significantly improving productivity by reducing the overall simulation burden.
3Measurement precision
If detailed analysis of each parasitic element is performed to achieve high measurement precision, then measurement precision is improved, but device complexity increases due to multiple simulation configurations
Solution Approach 1:
The patent extracts and identifies critical nets through initial simulation, then separates them from the rest of the circuit for focused detailed analysis. This extraction approach maintains high measurement precision for the most important elements while reducing the complexity burden by excluding non-critical nets from detailed simulation configurations.
Data Source
AI summary
According to one embodiment, a method for designing a semiconductor integrated circuit acquires a first simulation result by circuit simulation including a first kind of parasitic element and a second kind of parasitic element to be evaluated for a first net and a second net. A net selection circuit is generated including just one kind of parasitic element on one net selected from the first net and the second net and the two kinds of parasitic elements on the other nets, and a net selection simulation result is acquired by circuit simulation for each of the net selection circuits.