Semiconductor Parity Error Detection via ECC Encoding
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Solution Overview
Problem
As semiconductor devices increase in operating speed, ensuring data transmission reliability becomes challenging due to higher error probabilities, necessitating effective error detection and correction mechanisms.
Innovation Solution
A semiconductor system and device that utilize ECC encoding to generate and store parity information, allowing for error detection and repair flag signal generation, enabling the detection of errors and repair status through comparison circuits and fuse circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve productivity, then operating speed increases, but error probability increases reducing reliability
Solution Approach 1:
The patent applies preliminary action by generating and storing expected parity information through ECC encoding on addresses before actual data transmission occurs. This pre-computed parity is stored in a parity storage circuit and later used for error detection, allowing the system to maintain high transmission speeds while ensuring reliability through pre-prepared error checking data.
Solution Approach 2:
The patent implements feedback by comparing the stored expected parity information with actually received parity data after transmission. The comparison circuit generates failure information based on this feedback, enabling the system to detect transmission errors and trigger appropriate error handling, thus maintaining reliability despite high-speed operation.
2Reliability
If ECC encoding is performed on every address to generate parity information for error detection, then reliability improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by performing ECC encoding selectively only on address data rather than all transmitted data. The parity storage circuit stores parity information locally for each address, and the comparison circuit only compares parity for addresses that experience transmission errors. This localized approach provides error detection capability where needed while avoiding the complexity of processing all data through ECC encoding.
Solution Approach 2:
The patent extracts only the essential error detection function by separating parity generation, storage, and comparison into distinct dedicated circuits. The ECC encoding circuit generates parity, the parity storage circuit stores it, and the comparison circuit detects errors. This extraction of specific functions into specialized components achieves reliable error detection while keeping each component relatively simple and manageable.
Data Source
AI summary
A semiconductor system includes a controller configured to output parity information that includes an expected value at which an error correction code (ECC) encoding operation has been performed on an address in a test mode of a semiconductor device and configured to receive failure information. The semiconductor system also includes the semiconductor device configured to store an internal parity generated by performing the ECC encoding operation on the address that is input in a normal mode of the semiconductor device and configured to output the failure information generated by comparing the parity information and an output parity generated from the internal parity that is stored in the semiconductor device in the test mode.