Semiconductor Device With Partial Insulating Foil On Metal Carrier
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Solution Overview
Problem
The increasing complexity and function integration in semiconductor devices require innovative packaging solutions to shorten signal channel lengths, improve heat dissipation, robustness, and reduce manufacturing costs, while accommodating chips with different electric potentials on a single metal carrier.
Innovation Solution
A semiconductor device design featuring a metal carrier with an insulating foil that partially covers the carrier, allowing for the attachment of chips with different electric potentials, where one chip is electrically insulated from the carrier and the other is directly coupled, using a combination of adhesive and electrically conducting glues or soldering, with the foil's thickness and shape optimized for specific applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips with different electric potentials are mounted on a metal carrier, then electrical isolation is achieved, but the device complexity increases due to the need for insulating structures
Solution Approach 1:
The patent applies local quality by using a metal carrier that is selectively insulated in specific regions. The insulating layer is applied only to portions of the carrier where electrical isolation is needed, while leaving other regions exposed to provide electrical connection. This allows different chips to be mounted on the same carrier with different electrical isolation requirements, achieving reliable electrical isolation without unnecessarily complicating the entire device structure.
Solution Approach 2:
The patent segments the carrier surface into insulated and non-insulated regions, allowing different functional zones on the same carrier. This segmentation enables multiple chips with different electrical potential requirements to be mounted on a single carrier without requiring complete insulation of the carrier, thus reducing overall device complexity while maintaining necessary electrical isolation.
2Volume of moving object
If chips are placed closer together to reduce device size, then the device footprint is reduced, but heat dissipation becomes more difficult
Solution Approach 1:
The patent introduces a metal carrier as an intermediary thermal management structure between the chips and the environment. The carrier acts as a heat sink and thermal conduction path, collecting heat from multiple closely-spaced chips and dissipating it through its larger surface area and thermal mass. This intermediary structure enables closer chip placement while maintaining effective heat dissipation.
Solution Approach 2:
The patent merges the electrical connection function and thermal management function into a single metal carrier structure. The carrier simultaneously provides electrical connectivity to chips, mechanical support, and thermal dissipation. This consolidation allows chips to be placed closer together since the integrated carrier handles both electrical and thermal requirements, eliminating the need for separate thermal management structures that would increase device size.
3Ease of manufacture
If traditional packaging methods are used to accommodate increasing function integration, then manufacturing processes remain simple, but signal channel lengths cannot be shortened and heat dissipation is poor
Solution Approach 1:
The patent transitions from traditional two-dimensional planar packaging to a three-dimensional stacked architecture. Multiple chips are mounted vertically on the metal carrier in different layers, with interconnect structures providing electrical connections between layers. This dimensional change allows signal channels to be significantly shortened while accommodating increased function integration, and the metal carrier provides efficient thermal pathways in the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables closer chip placement, reducing device size, improving thermal management, and lowering production costs by using inexpensive, easily adaptable insulating materials, while maintaining electrical isolation and efficient heat transfer.
Implementation Method 1
an insulating foil (5) partially covering the metal carrier (3)
Implementation Method 2
using a combination of adhesive and electrically conducting glues or soldering
Implementation Method 3
using a combination of adhesive and electrically conducting glues or soldering
Data Source
AI summary
This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil.