Semiconductor Package Partial Plating Contact Side Surfaces
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Solution Overview
Problem
Conventional semiconductor packages face issues with corrosion and reduced solderability due to exposed copper surfaces on the side walls of contacts, which are not plated during the electroplating process, leading to potential oxidation and defects during assembly onto printed circuit boards.
Innovation Solution
The semiconductor package design incorporates partial plating on contact side surfaces, featuring a step structure where only the first and curved surfaces are plated, while the second surface remains exposed, ensuring quality soldering without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor array is electroplated with lead finished material before singulation, then the bottom surfaces of contacts are protected from oxidation, but the side walls of contacts remain exposed and susceptible to corrosion
Solution Approach 1:
The patent applies different surface treatments to different regions of the contact structure. The bottom surface receives electroplating for oxidation protection, while the side walls are selectively plated after singulation to provide corrosion protection. This local differentiation of protective measures resolves the contradiction between protecting against oxidation and preventing corrosion.
Solution Approach 2:
The electroplating of the bottom surface is performed as a preliminary action before singulation, ensuring oxidation protection is established early in the manufacturing process. This preliminary plating creates a foundation that protects the most critical surface from oxidation during subsequent handling and storage.
2Reliability
If all contact surfaces are plated, then complete oxidation protection is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of uniformly plating all contact surfaces, the patent selectively plates only the bottom surface before singulation and only the side walls after singulation. This localized approach to plating reduces manufacturing complexity while maintaining adequate oxidation protection where it is most needed.
Solution Approach 2:
The patent implements partial plating rather than complete plating of all contact surfaces. By applying plating only to specific regions (bottom surface initially, then side walls later), the manufacturing process becomes simpler and more cost-effective while still achieving the necessary protection levels.
3Ease of manufacture
If side walls are left unplated to simplify manufacturing, then production complexity is reduced, but solderability deteriorates due to oxidation
Solution Approach 1:
The patent performs preliminary electroplating of the bottom surface before singulation, establishing protection early. The side walls are then plated as a second preliminary action after singulation but before assembly, ensuring solderability is maintained without requiring continuous complex manufacturing processes.
Solution Approach 2:
The plating process is segmented into two distinct stages: pre-singulation plating of the bottom surface and post-singulation plating of the side walls. This segmentation allows each plating operation to be optimized independently, simplifying the overall manufacturing process while maintaining solderability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable soldering by preventing oxidation on plated areas and maintaining solderability even if the unplated areas are contaminated, enhancing the assembly process and reducing device failures.
Implementation Method 1
the contacts are plated with a lead finished material, such as matte tin (Sn), using electroplating
Data Source
AI summary
Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).