Semiconductor Sidewall Protection via Trench Grid and Parylene
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge is to protect the sidewalls of small semiconductor devices from solder material contact during packaging, which can lead to malfunction, especially when conventional packaging technologies are inadequate for handling tiny devices and ensuring sidewall isolation and preventing cracks.
Innovation Solution
A method involving the fabrication of semiconductor devices on a wafer, forming contact pads, creating an isolation layer, placing the wafer on a carrier with the backside facing up, etching a trench grid network, and applying a protective Parylene layer from the backside to demarcate device boundaries and prevent solder contact, followed by etching to remove the protective layer from horizontal surfaces and singulate the devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging technologies are used for small semiconductor devices, then device size can be reduced, but sidewalls remain unprotected and susceptible to solder material contact causing malfunction
Solution Approach 1:
A protective layer is deposited on the sidewalls of the semiconductor device before the soldering process. This preliminary protective coating prevents solder material from contacting and damaging the sidewalls during subsequent packaging and soldering operations, thereby maintaining device reliability while enabling miniaturization.
Solution Approach 2:
The protective layer acts as an intermediary substance between the solder material and the device sidewalls. This intermediate layer prevents direct contact between the potentially harmful solder material and the sensitive sidewall structures, allowing small devices to be packaged without sidewall damage.
2Length of moving object
If device size is reduced to millimeters or less, then electronic systems can be smaller, but unprotected sidewalls may touch solder material causing malfunction
Solution Approach 1:
The protective layer is applied to the sidewalls before soldering, creating a preliminary barrier that prevents solder material from contacting the sidewalls. This advance protection enables the use of smaller device dimensions without introducing the harmful effect of solder contact.
Solution Approach 2:
A thin film protective layer is formed on the sidewalls to provide protection against solder material contact. This flexible thin film coating covers the sidewall surface while allowing the device to maintain its small dimensional scale.
3Ease of manufacture
If sidewalls are left unprotected in small devices, then manufacturing process is simpler, but device malfunction occurs due to solder contact
Solution Approach 1:
The protective layer serves as an intermediary that prevents direct interaction between solder material and sidewalls. This intermediate barrier maintains device functionality and reliability while the overall packaging process remains relatively simple and integrated into existing manufacturing flows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for simultaneous packaging of multiple devices on a wafer, enhancing yield and reducing costs by preventing solder contact with sidewalls, thus improving system reliability and handling small device sizes effectively.
Implementation Method 1
The protective layer is deposited in gaseous form
Implementation Method 2
The protective layer is deposited in gaseous form. The protective layer is made of Parylene or similar type of material as conformal coating.
Implementation Method 3
etching to remove the protective layer from horizontal surfaces
Data Source
AI summary
A method of protecting sidewalls a plurality of semiconductor devices is disclosed. The method includes fabricating the plurality of semiconductor devices on a semiconductor wafer, etching to form a trench grid network on the backside of the semiconductor wafer. The trench grid network demarcate physical boundaries of each of the plurality of semiconductor devices. The method also includes depositing a protective layer on the backside and etching to remove the protective layer from horizontal surfaces and to singulate each of the plurality of semiconductor devices from the semiconductor wafer.


