Semiconductor Device Pass Voltage Control for Memory Cell Interference

Solution Overview

Problem

Semiconductor memory devices face challenges in efficiently programming memory cells without interference between adjacent cells, particularly when cells are stacked in three dimensions, leading to reduced data reliability and program characteristics.

Innovation Solution

A semiconductor device and method that control the application of pass voltages to adjacent memory cells based on the program target level of a selected cell, adjusting voltage levels to separate charge distributions and reduce interference, with first pass voltage having a higher level when the target level is below a threshold and a lower level when above, ensuring proper programming and data reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are stacked in three dimensions to increase storage capacity, then the quantity of stored data increases, but interference between adjacent cells increases and data reliability deteriorates

Engineering Contradiction:

Improvestorage capacityVSAvoiddata reliability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies different voltage levels to different adjacent memory cells based on their program target levels. When a selected memory cell has a low program target level, a first pass voltage is applied to a first adjacent memory cell and a second pass voltage is applied to a second adjacent memory cell, where the first pass voltage has a higher voltage level than the second pass voltage. This local differentiation of voltage application prevents charge distribution overlap and eliminates interference between adjacent cells in the three-dimensional stack.

Inventive Principle:

Principle #3Local quality

2Device complexity

If uniform pass voltage is applied to all adjacent memory cells during programming, then the device complexity is reduced, but interference between adjacent cells occurs and program characteristics deteriorate

Engineering Contradiction:

Improvecontrol complexityVSAvoidprogram characteristics

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent implements dynamic voltage control where the pass voltage applied to adjacent memory cells is adjusted based on the program target level of the selected memory cell. The control logic dynamically selects between different pass voltage schemes: when the program target level is low, a first pass voltage is applied to the first adjacent cell and a second pass voltage is applied to the second adjacent cell with different voltage levels; when the program target level is high, a different voltage scheme is applied. This dynamic adaptation optimizes programming characteristics without excessive complexity.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter of pass voltages applied to adjacent memory cells based on the program target level. Specifically, when the program target level is below a threshold, the first pass voltage is set to a higher voltage level than the second pass voltage; when the program target level is above the threshold, the voltage relationship is reversed or adjusted. This parameter change prevents charge distribution overlap and eliminates programming interference.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If high pass voltage is applied to prevent interference in adjacent cells, then data reliability improves, but energy consumption increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidenergy consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies different voltage levels to different adjacent memory cells based on their program target levels. When a selected memory cell has a low program target level, a first pass voltage is applied to a first adjacent memory cell and a second pass voltage is applied to a second adjacent memory cell, where the first pass voltage has a higher voltage level than the second pass voltage. This local differentiation of voltage application prevents charge distribution overlap and eliminates interference between adjacent cells in the three-dimensional stack.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11417376B2Semiconductor device and operating method of a semiconductor device

Publication Date: 2022.08.16 SK HYNIX INC

AI summary

A semiconductor device includes a memory string coupled between a source line and a bit line and including a plurality of memory cells, a plurality of word lines, a peripheral circuit configured to apply a program voltage to a word line, apply a first pass voltage to a word line coupled to a first memory cell adjacent to the selected memory cell, and apply a second pass voltage to a second memory cell adjacent to the selected memory cell, and control logic configured to control the peripheral circuit so that the first pass voltage has a higher voltage level than the second pass voltage when a program target level of the selected memory cell is lower than a first threshold value, and the first pass voltage has a lower voltage level than the second pass voltage when the program target level is higher than a second threshold value.