Semiconductor Device Passivation Adhesion via Composite Layers
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Solution Overview
Problem
In semiconductor wafer level packaging, poor adhesion between wiring redistribution layers and passivation layers, as well as between low k dielectric materials and metals, leads to reliability issues and peeling due to mechanical stress, affecting device performance and signal communication time.
Innovation Solution
The implementation of a semiconductor device structure that includes a conductive electrode, a passivation layer with through openings, a wiring redistribution layer with an Al layer and TiW interface, an Ni/Au layer for enhanced adhesion, and a solder mask, along with a manufacturing method that involves electro-deposition coating and sacrifice layers to form a stable passivation structure, which improves adhesion and reduces peeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If low k dielectric materials are utilized as dielectric layers between metal lines to decrease capacitance and improve circuit performance, then the capacitance value decreases and signal communication time improves, but the adhesive strength between the low k materials and metals decreases, causing ILD layers to peel due to mechanical stress
Solution Approach 1:
The patent employs composite material structures by combining low k dielectric materials with metal layers and adhesion promotion layers. The ILD layers are constructed as multi-layer composites including low k dielectric material, metal traces, and adhesion promotion layers, which collectively provide both low capacitance for fast signal communication and sufficient adhesion strength to prevent peeling under mechanical stress.
Solution Approach 2:
The patent introduces adhesion promotion layers as intermediary structures between the low k dielectric materials and metal layers. These adhesion promotion layers serve as mediators that enhance the bonding interface, allowing the low k dielectric layers to maintain both their low capacitance property and strong adhesion to metal interconnections, thereby preventing peeling during packaging and operation.
2Productivity
If the line pitch is decreased to increase circuit density and connect every individual element, then the circuit density increases, but the capacitance value increases and RC delay time increases, negatively affecting signal communication time
Solution Approach 1:
The patent changes the dielectric parameter by utilizing low k dielectric materials with dielectric constants less than 3.0, which is significantly lower than conventional silicon oxide materials. This parameter change in dielectric constant directly reduces the capacitance value between closely-spaced metal lines, thereby reducing RC delay time and enabling faster signal communication while maintaining high circuit density through decreased line pitch.
3Reliability
If conventional silicon oxide is utilized as ILD layers to provide adequate adhesion strength, then the adhesive strength between ILD layers and metals is sufficient, but the dielectric constant is high (4.0-4.5), increasing capacitance value and RC delay time
Solution Approach 1:
The patent transitions from using conventional silicon oxide ILD layers to composite ILD structures that incorporate low k dielectric materials. These composite structures combine low k dielectric layers with adhesion promotion layers and metal interconnections, achieving both low capacitance (fast signal communication) and sufficient adhesion strength through the synergistic combination of multiple materials with complementary properties.
Solution Approach 2:
The patent introduces adhesion promotion layers as intermediary structures between low k dielectric materials and metal interconnections. These intermediary layers resolve the adhesion deficiency of low k materials while preserving their low capacitance advantage, enabling the system to achieve both fast signal communication and reliable mechanical bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the adhesion between layers, increases the reliability of semiconductor devices, and reduces peeling from mechanical stress, thereby improving circuit performance and signal communication speed.
Implementation Method 1
a solution comprising an electro-deposition coating material is provided. Further, the semiconductor wafer is immersed into the solution. Thus, the electro-deposition coating material attaches to the metal layer beyond the sacrifice layer and a second surface opposing to the first surface of the semiconductor wafer, forming a second passivation film
Data Source
AI summary
A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.