Semiconductor Passivation Layer Stack for Voltage Blocking
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Solution Overview
Problem
Existing power semiconductor devices face challenges in maintaining a robust passivation layer that can withstand high electric fields and prevent degradation, especially in humid environments, which affects their voltage blocking capability.
Innovation Solution
A semiconductor device with a passivation layer stack comprising an amorphous semi-insulating layer, a first nitride layer, and a second nitride layer, along with an optional intermediate ductile layer and oxide layer, providing mechanical and chemical protection while preventing mechanical defects and covering defect regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional passivation layer (e.g., silicon dioxide) is used, then the device provides basic protection, but the mechanical and chemical robustness is insufficient under high electric fields and humid conditions
Solution Approach 1:
The patent employs a composite passivation layer structure consisting of multiple distinct layers: an amorphous semi-insulating layer (such as silicon carbide or silicon oxide) in direct contact with the semiconductor substrate, followed by one or more nitride layers (such as silicon nitride or tantalum nitride). This composite structure combines the advantages of each material—the amorphous layer provides excellent interface quality and electrical properties, while the nitride layers contribute superior mechanical strength and chemical inertness—thereby achieving enhanced overall reliability and robustness that neither material could provide alone.
2Reliability
If a single-layer passivation structure is used, then the device complexity is low, but the protection against mechanical defects and degradation is insufficient
Solution Approach 1:
The patent divides the passivation function into multiple separate layers, each with specific thicknesses and material compositions tailored to different protective functions. The amorphous semi-insulating layer is segmented from the nitride layers, with each layer optimized independently for its specific role—electrical passivation, mechanical protection, or chemical resistance. This segmentation allows each layer to be precisely controlled and optimized without compromising the overall structure.
Solution Approach 2:
The passivation structure is organized as a nested hierarchy where the amorphous semi-insulating layer forms the innermost layer directly protecting the semiconductor substrate, and the nitride layers are positioned as outer layers providing additional protection. This nested arrangement ensures that each layer protects the inner layers while maintaining a compact overall structure, with the most critical protection closest to the substrate.
Data Source
AI summary
A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.