Semiconductor Passivation Layer Stress Crack Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor fabrication processes face challenges in managing tensile stress between conductive features, which can lead to stress concentration zones and potential stress cracks in passivation layers, affecting the reliability and integrity of the semiconductor device.
Innovation Solution
A multiple-stage deposition process is employed to form dielectric blocking structures with passivation layers positioned outside the stress concentration zone, where tensile stress is highest, between 40% to 60% of the conductive feature height, to mitigate stress cracks and ensure structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passivation layers are deposited covering the entire conductive feature height, then complete coverage and protection is achieved, but stress concentration zones (40%-60% height) become vulnerable to stress cracks
Solution Approach 1:
The passivation layer is divided into multiple discrete layers positioned at different heights. The first passivation layer is positioned at a first height and the second passivation layer is positioned at a second height, creating a segmented structure that avoids concentrating stress at a single interface location.
Solution Approach 2:
The solution moves from a single-layer passivation approach to a multi-layer vertical arrangement. By positioning passivation layers at different heights (different vertical positions), the design adds dimensional distribution to avoid the stress concentration zone while maintaining complete coverage.
2Reliability
If a single passivation layer is used, then the structure is simple, but it cannot avoid stress concentration zones and is prone to cracking
Solution Approach 1:
The single passivation layer is segmented into multiple discrete layers at different heights. This segmentation allows each layer to be positioned independently outside stress concentration zones, improving reliability while the modular approach keeps the overall structure manageable.
Solution Approach 2:
Different passivation layers are positioned at different local heights to provide localized protection. The first passivation layer protects at its specific height while the second passivation layer protects at another height, with each layer having optimal positioning for its local stress environment.
3Ease of manufacture
If passivation layer interfaces are positioned at any height, then deposition is straightforward, but interfaces in the 40%-60% height range create stress cracks
Solution Approach 1:
The passivation layers are positioned in advance at specific heights that are predetermined to be outside the stress concentration zone. This preliminary positioning prevents stress cracks before they can occur, rather than attempting to repair or mitigate them after deposition.
Solution Approach 2:
The vertical position parameter of the passivation layers is changed from arbitrary or uniform positioning to specific height positioning. By controlling the vertical position parameter to be outside the 40%-60% height range, the stress crack resistance is improved while maintaining manufacturing feasibility.
Data Source
AI summary
A semiconductor device includes a first conductive feature and a second conductive feature. A first passivation layer is positioned between the first conductive feature and the second conductive feature. A second passivation layer is positioned between the first conductive feature and the second conductive feature and over the first passivation layer. A lowermost portion of an interface where the first passivation layer contacts the second passivation layer is positioned below 40% or above 60% of a height of the first conductive feature.