Semiconductor Passivation Trench Mitigates Dicing Stress

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Solution Overview

Problem

Conventional semiconductor structure fabrication methods lead to cracking and erosion of passivation layers during dicing, affecting the performance of protection ring structures due to inadequate mechanical strength and exposure to external forces.

Innovation Solution

A semiconductor structure with a trench in the passivation layer within the isolation region, which reduces the impact of external forces and prevents damage, combined with a buffer layer for enhanced mechanical strength, and a specific ratio of total thickness of the isolation structure and passivation layer to trench depth for optimal protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If protection rings are formed in functional regions between cutting path and device structure, then the effect of dicing force to device structures is reduced, but the passivation layer may crack and erode during dicing affecting protection structure performance

Engineering Contradiction:
Improveprotection structure performanceVSAvoidpassivation layer mechanical strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent introduces isolation regions that segment the substrate into discrete cell regions, separating the protection rings from the cutting paths. This segmentation prevents the propagation of dicing forces through the passivation layer to the protection structures, resolving the contradiction between maintaining protection structure integrity and withstanding dicing forces.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The isolation regions act as intermediary elements between the cutting paths and the protection rings. These isolation regions absorb and isolate the mechanical stresses generated during dicing, protecting the passivation layer and protection structures from harmful forces while allowing the protection rings to function effectively.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional fabrication methods are used, then manufacturing process is simple, but passivation layers are exposed to external forces causing cracking and erosion

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidexternal force exposure to passivation layer
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent implements preliminary protective actions by forming isolation regions and protection rings before the dicing process. These structures are prepared in advance to withstand and isolate the harmful forces that will be applied during subsequent dicing operations, preventing cracking and erosion of the passivation layer.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation regions serve as cushioning elements that are positioned beforehand to absorb and dissipate the mechanical impacts during dicing. This prior cushioning protects the passivation layer and protection structures from the harmful effects of external forces applied during the cutting process.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11094591B2Semiconductor structure and fabrication method thereof
Publication Date: 2021.08.17 SEMICON MFG INT (SHANGHAI) CORP
  • US11094591B2 patent drawing
  • US11094591B2 patent drawing
  • US11094591B2 patent drawing

AI summary

Semiconductor structures and fabrication methods are provided. An exemplary semiconductor structure includes a semiconductor substrate having a plurality of cell regions. Each of the cell regions includes a device region, a protection region surrounding the device region and an isolation region surrounding the device region and the protection region. The semiconductor structure also includes a device structure on the semiconductor substrate in the device region; a protection ring structure on the semiconductor substrate in the protection region; an isolation structure on the semiconductor substrate in the isolation region; a passivation layer on the protection ring structure, the device structure and the isolation structure; and a trench passing through the passivation layer in the isolation region.