3D Semiconductor Memory Passivation Layer Warpage Control
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Solution Overview
Problem
Semiconductor devices with vertical transistor structures face warpage issues during manufacturing due to heating, which can lead to reliability problems and increased integration challenges.
Innovation Solution
A 3-dimensional semiconductor memory device is designed with a passivation layer having first and second line patterns of different vertical thicknesses and widths, strategically arranged to control warpage by applying compressive and tensile stress, thereby reducing warpage in specific directions and enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical transistor structure is used to increase integration density, then the degree of integration is improved, but warpage occurs due to heating during manufacturing which reduces reliability
Solution Approach 1:
The passivation layer is divided into multiple regions with different thicknesses (first regions with first thickness, second regions with second thickness) that are arranged in a segmented pattern. This segmentation allows different portions of the passivation layer to apply different stress characteristics to the underlying substrate, enabling control of warpage in multiple directions simultaneously while maintaining high integration density of the vertical transistor structure
Solution Approach 2:
Different regions of the passivation layer are given different local qualities through varying thickness. The first regions have a first thickness and the second regions have a second thickness, creating local variations in stress application. This local quality differentiation enables targeted stress management at specific locations to counteract warpage caused by the vertical transistor structure fabrication process
2Ease of manufacture
If heating is applied during manufacturing to process the device, then manufacturing is completed, but warpage occurs which reduces reliability
Solution Approach 1:
The passivation layer structure is designed in advance to apply preliminary anti-action stress that counteracts the warpage-inducing stress generated during subsequent heating processes. The different thickness regions are configured to create opposing stress fields that preemptively counterbalance the thermal expansion and contraction forces that will occur during manufacturing heating, thereby preventing warpage before it occurs
Solution Approach 2:
The physical parameters of the passivation layer, specifically the thickness parameter, are changed across different regions to alter the stress characteristics. By varying the thickness parameter from first thickness in first regions to second thickness in second regions, the stress distribution parameter is modified to compensate for thermal stress during manufacturing heating processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The passivation layer effectively reduces warpage in one direction while maintaining or reducing warpage in another direction, improving the overall reliability and integration of the semiconductor device by managing thermal stress.
Implementation Method 1
strategically arranged to control warpage by applying compressive and tensile stress, thereby reducing warpage in specific directions
Data Source
AI summary
In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions. The plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.