Semiconductor Passivation Structure for Void-Free Wiring Gaps
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Solution Overview
Problem
As semiconductor devices continue to scale down, challenges arise in maintaining device performance and reducing fabrication costs due to increased complexity and defects, particularly in non-planar transistor architectures like FinFETs and GAAFETs, where voids and stress-related issues in passivation layers lead to weak points and cracking.
Innovation Solution
A method of forming semiconductor devices with a first insulating passivation layer having a side surface angle greater than 103° and a second passivation layer with compressive stress, which eliminates voids between wiring lines and compensates for tensile stress, thereby reducing pinholes and passivation layer cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional passivation layers are formed with standard deposition methods, then the fabrication process is simple and fast, but voids form between wiring lines creating weak points and cracking
Solution Approach 1:
The passivation layer is divided into multiple segments: a first passivation layer deposited conformally on wiring lines, and a second passivation layer filling the gaps between wiring lines. This segmentation eliminates voids while maintaining structural integrity and preventing cracking.
Solution Approach 2:
Different regions of the passivation structure receive different treatments: the first passivation layer is deposited with specific conformal coverage on wiring lines, while the second passivation layer is deposited to fill inter-wiring regions. This local differentiation ensures void-free coverage and stress distribution.
2Productivity
If device geometry is scaled down to increase functional density, then production efficiency increases and costs decrease, but device performance degradation and fabrication complexity increase
Solution Approach 1:
The solution transitions from a single-layer planar passivation approach to a multi-layer three-dimensional structure. The first passivation layer conforms to the wiring line surfaces, while the second layer fills the spaces between them, creating a void-free structure that maintains reliability at scaled dimensions.
3Reliability
If passivation layers are formed without stress compensation, then the fabrication process is simple, but tensile stress causes pinholes and cracking
Solution Approach 1:
The first passivation layer is deposited with controlled stress characteristics before the second passivation layer is added. This preliminary stress management prevents tensile stress accumulation that would otherwise cause pinholes and cracking, while keeping the fabrication process straightforward.
Data Source
AI summary
A semiconductor device includes a patterned wiring layer disposed above a semiconductor substrate, the patterned wiring layer including a plurality of wiring portions, and adjacent wiring portions being separated from each other. The semiconductor device also includes a first insulating passivation layer disposed over the wiring portions in a region between adjacent wiring portions, the first insulating passivation layer having a horizontal surface in the region between adjacent wiring portions. The semiconductor device further includes a second insulating passivation layer disposed on the first insulating passivation layer. The first insulating passivation layer and the second insulating passivation layer do not have a void in the region between adjacent wiring lines.