Semiconductor Circuit Pattern Layout for Precise Chip Placement
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Solution Overview
Problem
Pinpointing chip mounting positions is difficult and manufacturability is worsened when arranging semiconductor chips, leading to inefficiencies in semiconductor device assembly.
Innovation Solution
A semiconductor device design featuring a first circuit pattern with a recessed part and steps, where a second circuit pattern width increases downstream, and the recessed part width increases in a tiered manner, with semiconductor chips bonded onto the first pattern guided by these steps for precise positioning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor chips are arranged without specific positioning guides, then manufacturing process is simpler, but chip mounting position precision deteriorates
Solution Approach 1:
The first circuit pattern is segmented to include multiple steps at different heights, creating distinct positioning zones. These steps divide the mounting area into structured sections that guide chip placement, transforming a flat surface into a multi-level positioning structure without complicating the overall manufacturing process
Solution Approach 2:
The steps on the first circuit pattern serve as intermediary positioning guides between the mounting structure and the semiconductor chips. These intermediate structures provide reference surfaces that facilitate precise chip placement while maintaining manufacturing simplicity
2Reliability
If the second circuit pattern has uniform width, then manufacturing is easier, but electrical characteristics are unbalanced
Solution Approach 1:
The second circuit pattern is designed with non-uniform width where different sections have different widths to optimize electrical characteristics. The pattern width varies locally to balance electrical properties such as current distribution and parasitic inductance, rather than maintaining a uniform width throughout
Solution Approach 2:
The width parameter of the second circuit pattern is changed across different sections to achieve balanced electrical characteristics. By varying the width parameter spatially, the design optimizes electrical performance while the overall structure remains manufacturable
3Object-affected harmful factors
If wires are longer to connect chips to circuit patterns, then routing is simpler, but parasitic inductance and temperature rise increase
Solution Approach 1:
The circuit patterns are arranged in a three-dimensional configuration with steps at different heights, allowing wires to connect chips to circuit patterns in multiple spatial dimensions. This vertical arrangement reduces wire length by utilizing the Z-dimension, thereby decreasing parasitic inductance and temperature rise while maintaining routing simplicity
Data Source
AI summary
A semiconductor device includes: a first circuit pattern having a recessed part in a planar view; a second circuit pattern positioned in the recessed part; a plurality of semiconductor chips bonded onto the first circuit pattern; and wires connecting top electrodes of the plurality of semiconductor chips to the second circuit pattern, wherein a width of the second circuit pattern increases from upstream to downstream on a current path by which a current flows through the second circuit pattern, and the first circuit pattern has a step in a planar view on a side of the recessed part, and a width of the recessed part increases in a tiered way to match an increase in the width of the second circuit pattern.