Semiconductor Pattern Correction via Coverage Distribution Analysis
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Solution Overview
Problem
The miniaturization of semiconductor elements has outpaced the improvement in exposure device resolution, leading to deteriorated pattern transfer quality in lithography processes, resulting in error patterns that require significant effort to correct in design layouts.
Innovation Solution
A pattern correcting method that computes pattern coverage distribution near error patterns, identifies areas for adding addition patterns, generates candidates, and selects them based on predetermined criteria to minimize pattern density changes, thereby correcting the design layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual correction of design layout is performed to eliminate error patterns, then pattern transfer quality is improved, but the effort and time required for correction increases significantly
Solution Approach 1:
The design layout correction apparatus automatically performs correction by computing pattern coverage distribution and generating addition pattern candidates without requiring manual intervention. The system self-corrects the design layout by selecting and adding patterns that minimize coverage differences, eliminating the need for human effort in the correction process.
Solution Approach 2:
The apparatus changes the design layout parameters by computing pattern coverage distribution and determining addition pattern positions based on coverage differences. It automatically adjusts the design layout by adding patterns at specific locations to minimize coverage variations, thereby correcting error patterns through parameter optimization rather than manual editing.
2Stability of the object's composition
If addition patterns are added to correct design layout, then pattern coverage uniformity is improved, but the complexity of design layout increases
Solution Approach 1:
The apparatus applies local quality by computing pattern coverage distribution specifically in the vicinity of error patterns and generating addition pattern candidates only in those local areas. This targeted approach corrects coverage uniformity issues at critical locations without unnecessarily complicating the entire design layout, maintaining simplicity where patterns are already uniform.
Data Source
AI summary
A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.


