Semiconductor Pattern Density via Stacked Conformal Spacer Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The limitations of photolithography technology restrict the size and spacing of patterned structures in semiconductor devices, making it difficult to achieve high pattern density, which is essential for advanced semiconductor integrated circuit designs.
Innovation Solution
A manufacturing method involving multiple stacked conformal spacer layers and a covering layer is used on support features and a substrate, with specific etching processes to form a mask pattern with higher pattern density than the original support features, overcoming the resolution limitations of photolithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography technology is used to form patterned structures, then the manufacturing process is simple and straightforward, but the size and spacing between patterned structures are limited by exposure resolution minimum and cannot be further shrunk
Solution Approach 1:
The manufacturing process is segmented into multiple distinct stages: forming support features, depositing first and second conformal spacer layers, forming a covering layer, and performing selective removal processes. Each stage produces a specific structural component that contributes to the final high-density pattern, breaking down the complex task of achieving sub-resolution patterning into manageable steps.
Solution Approach 2:
The invention transitions from two-dimensional planar patterning to three-dimensional vertical structuring by forming multiple stacked conformal spacer layers (first conformal spacer layer, second conformal spacer layer) and a covering layer with different thicknesses. This vertical dimensionality allows the final etching process to generate horizontal patterns with density triple that of the original support features, effectively bypassing photolithography resolution limits.
2Manufacturing precision
If multiple stacked conformal spacer layers and covering layer are formed and selective removal processes are applied, then pattern density is increased beyond photolithography resolution limits, but the manufacturing process becomes more complex
Solution Approach 1:
The conformal spacer layers and covering layer are formed in advance with predetermined thickness relationships before the final etching step. The first conformal spacer layer is formed with a thickness greater than the second conformal spacer layer, and the covering layer is formed with a thickness greater than the first conformal spacer layer. This preliminary structuring enables the subsequent etching process to automatically generate the desired high-density pattern geometry without requiring complex real-time control.
Solution Approach 2:
The invention utilizes parameter changes in layer thicknesses to control the final pattern density. By setting the thickness of the covering layer greater than the first conformal spacer layer, and the first conformal spacer layer greater than the second conformal spacer layer, the selective removal process produces a mask pattern with triple the pattern density of the original support features. These parameter relationships are maintained throughout the manufacturing process to ensure consistent high-density patterning.
Data Source
AI summary
A manufacturing method of a patterned structure of a semiconductor device includes following steps. A plurality of support features are formed on a substrate. A first conformal spacer layer is formed on the support features and a surface of the substrate, a second conformal spacer layer is formed on the first conformal spacer layer, and a covering layer is formed on the second conformal spacer layer. A gap between the support features is filled with the first conformal spacer layer, the second conformal spacer layer, and the covering layer. A first process is performed to remove a part of the covering layer, the second conformal spacer layer, and the first conformal spacer layer. A second process is performed to remove the support features or the first conformal spacer layer between the support feature and the second conformal spacer layer to expose a part of the surface of the substrate.