Semiconductor Pattern Density Tile Design for Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration density of semiconductor devices leads to variations in pattern shapes and sizes due to differences in pattern density and perimeter, affecting the uniformity and precision of semiconductor device processing, necessitating a method to minimize these influences.
Innovation Solution
A method involving the formation of tiles with varying pattern densities and areas on a wafer, measuring and analyzing these patterns to determine a tile size with linear variation, and modifying the pattern density to unify layouts, such as unifying upper electrode patterns or modifying them into line-type, bar-type, or rim-type patterns, to achieve uniformity within a reference density range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of semiconductor devices is increased, then productivity and device capacity are improved, but pattern uniformity and processing precision deteriorate due to variations in pattern density and perimeter
Solution Approach 1:
The patent applies local quality by dividing the semiconductor wafer into multiple tiles with different pattern densities. Each tile is processed independently with its own density optimization, allowing high integration density in some regions while maintaining pattern uniformity in others. This resolves the contradiction by making pattern density a local rather than global property.
Solution Approach 2:
The patent changes the pattern density parameter across different tiles to achieve optimal processing results. By varying the pattern density parameter locally in different tiles while maintaining linear variation characteristics, the patent enables high overall integration density while preserving pattern uniformity within each tile's processing zone.
2Quantity of substance
If pattern density varies across different regions, then integration capacity is improved, but pattern shape and size uniformity deteriorate
Solution Approach 1:
The patent segments the semiconductor device pattern into multiple independent tiles, each with controlled pattern density. This segmentation allows different regions to have different integration capacities while maintaining uniform pattern shapes and sizes within each segment, resolving the contradiction between overall integration capacity and local pattern uniformity.
Solution Approach 2:
The patent implements local quality by assigning specific pattern densities to specific tiles based on their intended function and location. This allows the pattern shape and size to remain uniform within each tile while the overall device achieves high integration capacity through varied local densities.
3Productivity
If pattern density is increased to improve integration, then device capacity is improved, but processing precision and pattern consistency deteriorate
Solution Approach 1:
The patent optimizes the pattern density parameter by establishing a linear variation relationship between pattern size and density. This controlled parameter change ensures that even as integration density increases, the measurements remain consistent and predictable, resolving the contradiction between high integration and measurement precision.
Data Source
AI summary
A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design size and pattern density, and modifying the pattern density of the determined tile.