Semiconductor Pattern Design Timing Convergence
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Solution Overview
Problem
Current pattern designing methods for semiconductor circuits require repetitive calculations to ensure layout fidelity and timing convergence, leading to increased processing time and resource consumption, especially due to process dispersion affecting resistance and capacitance values.
Innovation Solution
A method involving transfer simulation and step simulation calculations using physical layout data to compare results with preset standards, reflecting dispersion in process parameters to quickly adjust electrical characteristics calculations, thereby reducing the need for repetitive corrections and optimizing the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional pattern designing methods are used to ensure layout fidelity and timing convergence, then manufacturing precision is improved, but processing time increases due to repetitive calculations
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing resistance and capacitance values for various pattern configurations in a lookup table before actual design processing. During timing verification, these pre-computed values are directly retrieved rather than recalculated, significantly reducing processing time while maintaining manufacturing precision for layout fidelity and timing convergence
Solution Approach 2:
The patent creates a simplified model or representation of electrical characteristics by storing computed resistance and capacitance values in a database structure. This copied information serves as a reference that can be quickly accessed during design iterations, avoiding repeated complex calculations while preserving the essential electrical behavior for timing verification
2Reliability
If traditional pattern designing methods are used to ensure timing convergence, then reliability is improved, but productivity decreases due to increased design hours
Solution Approach 1:
The patent performs preliminary computation of resistance and capacitance values for different pattern geometries and stores them in advance. During timing verification, these pre-computed electrical characteristics are retrieved from storage, enabling rapid assessment of timing convergence without repeating computationally intensive calculations, thus improving productivity while maintaining reliability
Solution Approach 2:
The patent implements feedback by using the stored resistance and capacitance values to quickly evaluate timing characteristics during design iterations. The system compares timing results against convergence criteria and provides feedback for design adjustments, enabling efficient iterative optimization that maintains timing convergence reliability while reducing overall design time
3Manufacturing precision
If process dispersion is considered in capacitance value extraction, then manufacturing precision is improved, but device complexity increases due to additional calculations
Solution Approach 1:
The patent applies preliminary action by pre-calculating capacitance values for various pattern configurations considering process dispersion effects, and storing these results in a database. During actual design processing, these pre-computed values are retrieved directly, achieving high manufacturing precision for capacitance extraction without requiring complex real-time calculations, thus reducing device complexity
Solution Approach 2:
The patent introduces an intermediary database or lookup table that stores pre-computed resistance and capacitance values. This intermediary structure acts as a mediator between complex electrical characteristic calculations and the actual design verification process, enabling accurate consideration of process dispersion effects while simplifying the operational complexity during timing verification
Data Source
AI summary
A pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset standard; and carrying out calculation for electrical characteristics by using parameters obtained from the physical layout when as a result of the comparison, the preset standard is fulfilled, and carrying out calculation for the electrical characteristics by reflecting the result of the transfer simulation calculation and the step simulation calculation in the parameters when as the result of the comparison, the preset standard is not fulfilled, thereby extracting the parameters.