Semiconductor Pattern Formation Using Aperiodic Dummy Structures
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Solution Overview
Problem
In semiconductor device manufacturing, periodic patterns such as line-and-space patterns face dimensional errors due to differing environmental influences on end and central patterns during the manufacturing process, leading to potential errors in the proximity effect.
Innovation Solution
A method involving the formation of aperiodic select gate patterns and dummy patterns between periodic word lines, where the dummy patterns are electrically independent and equalize the peripheral environment for both end and central line patterns, using a process that includes forming resist patterns, processing films, and selectively removing periodic patterns to create side wall patterns that function as masks for forming target patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If periodic patterns are formed using conventional photolithography, then wiring patterns can be created, but dimensional errors occur due to proximity effect influencing end and central patterns differently
Solution Approach 1:
The patent applies local quality by making end patterns aperiodic while keeping central patterns periodic. This local differentiation allows end patterns to have different dimensional specifications than central patterns, compensating for the additional proximity effect they experience. The aperiodic end patterns are designed with adjusted dimensions to achieve uniform overall pattern dimensions despite varying environmental influences.
Solution Approach 2:
The patent introduces asymmetry by designing end patterns that are aperiodic rather than periodic like the central patterns. This asymmetric treatment of end patterns versus central patterns allows for compensation of the proximity effect that differently impacts these regions. The dummy patterns are also asymmetrically positioned between word lines and select gates to equalize the peripheral environment.
2Manufacturing precision
If dummy patterns are added to equalize peripheral environment, then dimensional errors are suppressed, but chip area increases
Solution Approach 1:
The dummy patterns are strategically placed only where needed - specifically between word lines and select gates at the ends of the array - rather than uniformly across the entire chip. This localized application of dummy patterns provides the necessary dimensional error suppression only in regions where proximity effect variations occur, minimizing unnecessary area consumption.
Solution Approach 2:
The dummy patterns are designed and positioned in advance during the pattern design phase to pre-compensate for proximity effect variations. By preliminarily establishing the peripheral environment equalization through dummy pattern placement, the actual pattern formation process proceeds without dimensional errors, avoiding the need for additional correction steps or larger safety margins that would increase chip area.
Data Source
AI summary
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.