Semiconductor Pattern Layout With Pre-Routing Dummy Fill Isolation
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, requiring stricter specifications and reliability, particularly in generating and optimizing standard cell layout designs efficiently, while existing methods like post-dummy-fill techniques require significant manual work and do not guarantee electrical capacitance before routing.
Innovation Solution
The method involves generating a dummy pattern first, which reduces manual work and allows for the determination of the pattern and space between the dummy pattern and routed traces before routing, ensuring electrical capacitance and design requirements are met, by placing pins, conductive patterns, interconnection patterns, and cut patterns to form an isolated pattern that can be electrically floating or connected to a circuit pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If post-dummy-fill techniques are used, then manual work is reduced, but electrical capacitance cannot be guaranteed before routing
Solution Approach 1:
The patent applies preliminary action by performing dummy fill during the placement phase before routing occurs. This allows the pattern and space between dummy patterns and routed traces to be determined in advance, ensuring electrical capacitance requirements are met before the routing process begins, thus resolving the contradiction between reducing manual work and guaranteeing electrical capacitance.
2Area of moving object
If miniaturization is pursued, then device size decreases and power consumption reduces, but design and manufacturing specifications become stricter
Solution Approach 1:
The patent performs dummy fill placement before routing, allowing preliminary determination of patterns and spacing to meet stricter design specifications. This preliminary action ensures that even with miniaturization, the design can accommodate tighter manufacturing tolerances by pre-establishing the spatial relationships between dummy patterns and future routed traces.
Data Source
AI summary
A method and system of arranging patterns of a semiconductor device are provided. The method includes placing a first pin and a second pin. The method also includes generating a plurality of first conductive patterns. The method further includes selecting a first set of the plurality of first conductive patterns. In addition, the method includes placing a plurality of interconnection patterns to connect the first pin, the first set of the plurality of first conductive patterns, and the second pin. The method also includes placing cut patterns overlapping the first set of the plurality of first conductive patterns to form an isolated pattern including the first pin, the first set of the plurality of first conductive patterns, and the second pin.