Semiconductor Pattern Formation Using Spacer-Assisted Selective Etching
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Solution Overview
Problem
Current semiconductor manufacturing techniques face limitations in minimizing the critical dimension of patterns formed during photolithography, necessitating a technology that can exceed the resolution of conventional photolithography processes.
Innovation Solution
A method involving the formation of an etch target layer, followed by the creation of pre-patterns with pad portions and line forming portions, where spacers are used to form a blocking layer that exposes the line forming portion, allowing for the etching of bit line structures with pad portions that protrude and line portions, enabling the formation of fine patterns and preventing punch effects during contact hole formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography process is used, then manufacturing process is simple, but critical dimension of pattern cannot be minimized
Solution Approach 1:
The manufacturing process is divided into multiple stages: first forming pad portions with initial patterns, then forming spacers on sidewalls, and finally forming line portions through selective etching. This segmentation allows achieving finer critical dimensions by breaking down the single-step photolithography process into multiple controlled steps, each contributing to the final precise pattern.
Solution Approach 2:
Pad portions are formed in advance before the line portions. The preliminary formation of pad portions with protruding structures provides a foundation for subsequent spacer formation and selective etching, enabling precise control of critical dimensions that would be difficult to achieve with conventional direct photolithography.
2Manufacturing precision
If spacers are formed to minimize critical dimension, then pattern precision is improved, but parasitic capacitance increases
Solution Approach 1:
Different regions of the pattern have different properties: pad portions have larger width to reduce parasitic capacitance, while line portions have minimized width for precise patterning. The spacer structures are strategically positioned to provide mechanical support and electrical isolation where needed, while maintaining minimal capacitance in critical signal paths. This local differentiation resolves the contradiction between precision and parasitic effects.
3Ease of manufacture
If contact holes are formed directly without pad portions, then process is simpler, but punch effect occurs causing material exposure and leakage
Solution Approach 1:
Pad portions are formed in advance before contact hole formation. These preliminary pad structures protrude from the line portions and provide a larger target area for contact hole alignment, preventing the punch effect where contact holes might misalign and expose underlying materials. The pre-formed pads ensure reliable electrical connectivity while maintaining process feasibility.
Solution Approach 2:
The protruding pad portions act as a cushion or buffer zone that compensates for potential alignment variations during contact hole formation. By providing extra material and a larger target area, the pad portions beforehand cushion against misalignment, preventing punch effects and ensuring reliable contact plug connectivity without requiring excessively tight process control.
Data Source
AI summary
A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.