Semiconductor Pattern Transfer with Gap-Filling Core Layer Planarization
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Solution Overview
Problem
The uneven distribution of core layers in semiconductor manufacturing leads to recesses on the spin-coated hard mask layer, causing over-etching and pattern transfer errors, which reduces the reliability and yield of semiconductor chips.
Innovation Solution
A manufacturing method involving the formation of a substrate with a first core layer having an inclined sidewall and a smaller top dimension, followed by a dielectric layer and a filling layer to cover and protect the core layer, preventing over-etching and ensuring accurate pattern transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If core layers are formed with uneven distribution, then the manufacturing process can be simplified, but recesses are formed on the spin-coated hard mask layer causing over-etching and pattern transfer errors
Solution Approach 1:
A planarization layer is formed beforehand to fill the gaps between sparsely distributed core layers, creating a flat surface for the spin-coated hard mask layer. This preliminary action prevents recess formation and subsequent over-etching, maintaining pattern transfer accuracy while allowing simplified core layer formation
Solution Approach 2:
The planarization layer acts as an intermediary between the uneven core layer distribution and the spin-coated hard mask layer. It mediates the surface topology by filling凹陷 areas, ensuring uniform mask layer formation and preventing etching errors in the target material layer
2Device complexity
If the spin-coated hard mask layer is used directly over sparsely distributed core layers, then the manufacturing steps are reduced, but over-etching occurs in concave areas leading to pattern transfer errors
Solution Approach 1:
The planarization layer is deposited in advance to create a flat surface before forming the spin-coated hard mask layer. This preliminary planarization prevents over-etching in concave areas, ensuring reliable pattern transfer and maintaining high chip yield without adding excessive manufacturing complexity
Solution Approach 2:
The planarization layer serves as a cushioning layer that compensates for the uneven core layer distribution beforehand. It prevents the formation of recesses that would otherwise lead to over-etching, thereby cushioning against potential pattern transfer errors and reliability issues
Data Source
AI summary
A manufacturing method of a semiconductor structure includes: providing substrate including array area and peripheral area, where peripheral area includes mark area and blank area adjoining mark area; forming, on substrate, target layer and first core layer disposed on target layer, first core layer including first array core layer disposed on array area, first mark core layer disposed on mark area and first cap layer disposed on blank area, where first cap layer has inclined sidewall, and its top dimension is smaller than its bottom dimension; forming first dielectric layer covering sidewall of first core layer; forming first filling layer covering surface of first dielectric layer and filling gap in first core layer; and etching first dielectric layer and target layer along sidewalls of first array core layer and first mark core layer to transfer pattern of first core layer and pattern of first filling layer to target layer.