Semiconductor Patterning Method Using Hard Mask and Spacer Etching
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Solution Overview
Problem
Conventional photolithography processes are limited in achieving smaller critical dimensions for semiconductor device fabrication, necessitating a method to form smaller patterns simultaneously for bit line and pad portions.
Innovation Solution
A method involving the formation of preliminary patterns with plate and pad portions, followed by the creation of hard mask patterns and spacers to etch line patterns coupled to pad portions, allowing for the simultaneous formation of bit line and pad portions through a comb-shaped opening process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography process is used, then the patterning process is simple, but the critical dimension cannot be reduced below a certain limit
Solution Approach 1:
The patterning process is divided into multiple stages: forming preliminary patterns with pad portions, forming first and second hard mask patterns, forming spacers, and performing selective etching. This segmentation allows achieving smaller critical dimensions by breaking down the complex patterning into manageable steps, each optimizing for specific dimensional control
Solution Approach 2:
Preliminary patterns including pad portions are formed in advance before the main line patterns. The pad portions are prepared with appropriate spacing and positioning beforehand, allowing subsequent hard mask and spacer formation to achieve precise critical dimensions for the bit line portions without compromising pad integration
2Productivity
If separate formation processes are used for bit line and pad portions, then each portion can be optimized, but the overall fabrication time increases
Solution Approach 1:
The method combines the formation of bit line portions and pad portions into a single integrated process flow. By forming preliminary patterns with both pad portions and line portions simultaneously, then using shared hard mask and spacer formation steps, the patent achieves precise patterning for both structures without requiring separate fabrication sequences, thereby reducing overall fabrication time while maintaining high precision
3Manufacturing precision
If the critical dimension is reduced, then device density increases, but the bridge margin between neighboring patterns decreases
Solution Approach 1:
The patent applies different spacing requirements to different regions: larger spacing is maintained for pad portions to ensure reliable electrical connection and adequate bridge margin, while smaller spacing is utilized for the bit line portions to achieve high density. The hard mask and spacer formation processes are locally optimized to preserve bridge margins in critical areas while enabling reduced dimensions in line portions
Data Source
AI summary
A method for forming a pattern includes: forming a preliminary pattern having a plate portion and a plurality of pad portions that protrude from an end of the plate portion over a substrate; forming a first hard mask pattern that includes a blocking portion covering the pad portions and a plurality of line portions partially covering the plate portion; forming a spacer on a sidewall of each of the line portions; forming a second hard mask pattern that fills a space between the line portions by contacting the spacer; forming an opening that exposes the plate portion between the first hard mask pattern and the second hard mask pattern by removing the spacer; and forming a plurality of line pattern portions that are respectively coupled to the pad portions by etching an exposed portion of the plate portion through the opening.