Semiconductor Pattern Transfer With Anti-Reflection Layer Pitch Fixing
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Solution Overview
Problem
As semiconductor manufacturing advances towards higher integration levels, the photolithography process faces challenges in controlling line width roughness (LWR) and line edge roughness (LER), which adversely affect device performance due to the increasing critical dimension (CD) of semiconductor structures.
Innovation Solution
A method involving the sequential formation of an initial mask layer, an anti-reflection layer, and a patterned structure, followed by a first etching process to remove a surface portion of the anti-reflection layer, a surface treatment process to improve pattern smoothness, and a second etching process to expose the initial mask layer, ensuring the anti-reflection layer's bottom portion fixes the pattern's pitch, thereby maintaining consistent line width during subsequent etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the critical dimension is reduced to achieve higher integration levels, then information storage capacity increases, but line width roughness adversely affects device performance
Solution Approach 1:
A surface treatment process is performed on the patterned structure before the etching process to smooth the surface and reduce line width roughness. This preliminary action prepares the patterned structure in advance to prevent LWR from adversely affecting device performance during subsequent etching operations.
Solution Approach 2:
The anti-reflection layer serves as an intermediary between the patterned structure and the etching process. By controlling the etching of the anti-reflection layer and maintaining its bottom portion, the pattern's pitch is fixed, which prevents pattern displacement and maintains consistent line width during etching, thereby reducing LWR.
2Manufacturing precision
If the photolithography process is used to control critical dimension, then pattern formation is achieved, but line edge roughness deteriorates with smaller dimensions
Solution Approach 1:
The surface treatment process is applied to the patterned structure before etching to smooth the surface and reduce line edge roughness. This preliminary preparation ensures that the patterned structure has reduced LER before the etching process begins, improving the reliability of the final semiconductor device.
Solution Approach 2:
The anti-reflection layer acts as a mediator that protects the patterned structure during etching. By fixing the pitch through the bottom portion of the anti-reflection layer and controlling its etching, pattern displacement is prevented, which reduces line edge roughness and improves the reliability of the etched features.
3Productivity
If multiple etching processes are performed to transfer the pattern, then the target layer is successfully etched, but pattern displacement occurs affecting line width consistency
Solution Approach 1:
The anti-reflection layer serves as a protective intermediary during the etching process. By controlling the etching of the anti-reflection layer and maintaining its bottom portion, the pattern's pitch is fixed, which prevents pattern displacement and maintains consistent line width during subsequent etching operations.
Solution Approach 2:
A surface portion of the anti-reflection layer is selectively removed through the first etching process, while the bottom portion is preserved to maintain the pattern's pitch. This selective extraction allows the patterned structure to be protected from displacement during etching while still enabling successful pattern transfer to the target layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves line width roughness (LWR) and ensures the pattern's size consistency with the target, enhancing semiconductor device performance by preventing pattern displacement and maintaining expected dimensions during etching.
Implementation Method 1
the surface treatment process performed on the patterned structure includes a plasma treatment process
Implementation Method 2
each of the first etching process and the second etching process includes a dry etching process
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor structure. The method includes providing a target etching layer; sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer; performing a first etching process on the anti-reflection layer to remove a surface portion of the anti-reflection layer using the patterned structure as a mask; performing a surface treatment process on the patterned structure; and performing a second etching process on the anti-reflection layer until exposing a surface of the initial mask layer.