Semiconductor Pattern Fabrication via Region Segmentation
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Solution Overview
Problem
The fabrication of DRAM cells with buried gates is limited by defects due to limitations in fabrication technologies, leading to challenges in achieving enhanced performance and reliability.
Innovation Solution
A method is developed to form a layout definition of a semiconductor device using a photomask design that creates a compact, condensed layout by defining a core region and a periphery region, with patterns formed only in the first region and not in the second region, allowing for better photoresist layer permeation and easier removal, thereby avoiding photoresist layer filling in gaps and increasing process yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photomask patterns are formed in both core region and periphery region, then complete device definition is achieved, but photoresist layer fills gaps and becomes difficult to remove
Solution Approach 1:
The substrate is divided into two distinct regions: a first region where photomask patterns are formed and a second region where no patterns are formed. This segmentation allows the photoresist layer to be applied and removed selectively, solving the problem of photoresist accumulation in gap areas while maintaining precise device definition in the patterned region.
Solution Approach 2:
Different regions of the substrate are given different properties: the first region receives photomask patterns for precise device definition, while the second region remains pattern-free to avoid photoresist filling issues. This local differentiation resolves the contradiction between complete definition and ease of manufacturing.
2Ease of manufacture
If conventional planar gate structure is used, then fabrication is simpler, but current leakage from capacitor cannot be reduced
Solution Approach 1:
Instead of using the conventional planar gate structure where the gate is on top, the invention inverts the structure by placing the gate beneath the capacitor (buried gate structure). This inversion effectively reduces current leakage from the capacitor while the self-aligned fabrication process maintains manufacturing simplicity.
3Productivity
If element patterns are formed with larger line width and space, then optical exposure is easier, but device integration level cannot be increased
Solution Approach 1:
The invention transitions from two-dimensional planar patterning to three-dimensional self-aligned patterning by forming patterns in stacked layers. This dimensional change allows finer line widths and spacing to be achieved while maintaining manufacturing feasibility through the self-aligned process that eliminates the need for multiple alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of improved semiconductor devices, such as DRAM devices, with finer line widths and spaces, enhancing performance and reliability while simplifying the process flow and increasing yield by preventing photoresist layer issues in the second region.
Implementation Method 1
Since the gap fill ability of the photoresist layer is better, it is easy to permeate into the small gap between the patterns
Implementation Method 2
A first etching step is performed, to remove a portion of the first material layer in the first region... a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer
Data Source
AI summary
The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.