Semiconductor Pattern Transfer Layout for Reverse SADP Loading Effects
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Solution Overview
Problem
The Reverse SADP process experiences pattern defects in the array region and the peripheral region due to the significant difference in pattern density and height, causing a loading effect that results in target patterns deviating from the expected effect.
Innovation Solution
A semiconductor structure fabrication method that involves forming specific pattern mask layers with different dimensions and densities for the array and peripheral regions, followed by the formation of sacrificial layers and filling layers to control the etching process and reduce the height difference between regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the Reverse SADP process is used to fabricate patterns in array region and peripheral region, then the pattern density is increased, but the loading effect causes target patterns to deviate from expected effect due to significant difference in pattern density and height between regions
Solution Approach 1:
The patent applies local quality by forming different pattern mask layers with different pattern dimensions for different regions. Specifically, a first pattern mask layer with a first pattern dimension is formed for the array region, and a second pattern mask layer with a second pattern dimension is formed for the peripheral region. This allows each region to have optimized pattern dimensions suitable for its specific requirements, thereby resolving the loading effect caused by uniform patterning across regions with different density requirements.
Solution Approach 2:
The patent segments the patterning process into multiple steps with different mask layers. Instead of applying a single patterning process to both array and peripheral regions, the method divides the substrate into regions and applies region-specific pattern mask layers. This segmentation allows independent optimization of pattern dimensions for each region, eliminating the mutual interference that causes pattern deviation.
2Adaptability or versatility
If there is a significant difference in pattern density between array region and peripheral region, then the fabrication process becomes more challenging, but the height difference between regions causes loading effect
Solution Approach 1:
The patent addresses the height difference issue by forming different pattern mask layers with different pattern dimensions for different regions. The first pattern mask layer for the array region and the second pattern mask layer for the peripheral region are specifically designed to account for the height difference, ensuring that etching and other subsequent processes proceed uniformly across regions despite the underlying height variations.
Solution Approach 2:
The patent performs preliminary action by forming the pattern mask layers before the main fabrication process. By pre-establishing region-specific mask layers with appropriate pattern dimensions, the method prepares the structure in advance to withstand the loading effects that will occur during subsequent processing, thereby improving fabrication reliability.
Data Source
AI summary
Embodiments provide a semiconductor structure and fabrication method. The method include: forming sacrificial layers on a sidewall of the first pattern mask layer and a sidewall of the second pattern mask layer, and forming a first filling layer filling a first spacing between the sacrificial layers; removing the first filling layer, the first pattern mask layer and the second pattern mask layer, retaining the sacrificial layers and the first spacing, and replacing a second spacing between the first pattern mask layer and the second pattern mask layer; forming a second filling layer filling the first spacing and the second spacing; etching the sacrificial layers based on the second filling layer to form etched patterns, and etching the pattern transfer layer and the target layer based on the etched patterns to form a first pattern target layer in the array region and a second pattern target layer in the peripheral region.