Semiconductor Pattern Line Width Shrinkage via Sacrificial Layer
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Solution Overview
Problem
Conventional lithography processes struggle to achieve nanometer-scale semiconductor devices with differentiated line widths, leading to resolution limitations and integrity issues in pattern formation.
Innovation Solution
A method involving the formation of a sacrificial structure layer on a semiconductor pattern through reaction of its surface portion, followed by removal of the barrier and sacrificial layers, allowing for controlled shrinkage of the pattern line width without damaging the semiconductor device, enabling the creation of semiconductor patterns with differentiated line widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used to fabricate nanometer-scale semiconductor devices, then the manufacturing process is simple and well-established, but the resolution limitation prevents achieving differentiated line widths and pattern integrity is compromised
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming barrier patterns on specific regions, selective surface reaction to create sacrificial structure layers, and sequential removal steps. This segmentation allows different line widths to be fabricated through controlled processing steps rather than requiring a single high-resolution lithography step, thereby achieving differentiated line widths while managing process complexity.
Solution Approach 2:
Barrier patterns are formed in advance on specific semiconductor patterns before the actual line width differentiation is needed. This preliminary action prepares the structure for subsequent selective processing, enabling precise control over which patterns will be shrunk and by how much, thus achieving high manufacturing precision for differentiated line widths.
2Reliability
If the line width of semiconductor patterns is shrunk to achieve nanometer-scale devices, then the electrical performance is improved, but the pattern integrity may be damaged during the shrinking process
Solution Approach 1:
A sacrificial structure layer is introduced as an intermediary between the barrier pattern and the final shrunk pattern. This sacrificial layer is formed by selective surface reaction and is subsequently removed, allowing the semiconductor pattern to be shrunk to the desired nanometer scale without direct damage. The intermediary layer protects the pattern integrity during the shrinking process while enabling the achievement of high electrical performance through precise line width control.
3Manufacturing precision
If a sacrificial structure layer is formed and removed to achieve fine shrunk patterns, then the line width precision is improved, but the fabrication process steps increase
Solution Approach 1:
Multiple functions are merged into the sacrificial structure layer formation step: the surface reaction simultaneously creates the sacrificial layer and defines the shrunk pattern geometry. The subsequent removal of the barrier pattern and sacrificial layer is combined into a single etching step, reducing the overall process complexity despite the added precision capability. This merging approach maintains productivity while achieving high line width control precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of nanometer-scale semiconductor devices with high electrical performance by achieving fine, shrunk patterns with controlled line widths, overcoming the limitations of conventional lithography and maintaining pattern integrity.
Implementation Method 1
a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer
Data Source
AI summary
A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.