Semiconductor Pattern Formation Using Sacrificial Layer Etching
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Solution Overview
Problem
The reduction of design rules in semiconductor memory devices necessitates advanced technologies for forming precise metal lines and patterns, where existing methods face challenges in overcoming photolithography resolution limits and achieving uniform trench formation.
Innovation Solution
A method involving multiple mask layers and a sacrificial layer is employed to form parallel trenches in a semiconductor substrate, where a first mask layer pattern is formed with parallel lines, a sacrificial layer is added between these lines, and a third mask layer pattern covers the ends and creates openings between the lines, allowing for etching to form parallel trenches, which can be filled with a conductive layer like copper.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography stepper is used to form minute patterns, then manufacturing process is simple, but resolution limit prevents formation of sufficiently small features
Solution Approach 1:
The fabrication process is divided into multiple stages: first forming a preliminary pattern with the photolithography stepper, then using etching processes to create final high-resolution patterns. This segmentation allows the simple photolithography step to be combined with precise etching to overcome the resolution limit while maintaining overall process simplicity.
Solution Approach 2:
A preliminary pattern is formed first using photolithography, which then serves as a template for subsequent etching processes. This preliminary action enables the final high-resolution pattern to be achieved through etching rather than directly through photolithography, bypassing the resolution limit.
2Productivity
If design rules are reduced to increase device density, then productivity increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent replaces direct photolithographic pattern formation with an etching-based pattern formation process. The photolithography step only needs to create a low-resolution preliminary pattern, while the final high-resolution patterns are formed through controlled etching processes, thereby decoupling device density from photolithography resolution requirements.
3Manufacturing precision
If multiple mask layers are used to form precise patterns, then manufacturing precision improves, but device complexity and process steps increase
Solution Approach 1:
The patent merges the pattern formation function into a single integrated process: photolithography creates a preliminary pattern that directly serves as the mask for subsequent etching steps. This eliminates the need for separate mask layers and multiple patterning steps, achieving high precision while reducing overall process complexity.
Solution Approach 2:
The preliminary photolithographic pattern formation serves dual purposes: it defines the initial pattern geometry and simultaneously acts as the mask for the etching process. This preliminary action consolidates multiple functions into one step, reducing the number of required process steps while maintaining high pattern precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of precise, uniform parallel conductive lines within the semiconductor device, improving pattern resolution and reducing the complexity of the fabrication process by using a sacrificial layer and multiple mask layers to overcome photolithography limitations.
Implementation Method 1
The sacrificial layer and the etch target layer are etched using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches
Data Source
AI summary
A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends. The sacrificial layer and the etch target layer are etched using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches in the etch target layer between the line portions of the first and second mask layer patterns. Conductive lines may be formed in the trenches.